DS643 Datasheet, PDF (199/216 Pages) Xilinx, Inc – Soft Direct Memory Access (SDMA) support

LogiCORE IP Multi-Port Memory Controller (v6.06.a)
Notes on PLB PIM Throughput
The PLB PIM latency is measured from PAValid of the first PLB transaction to when the first PLB_wrDAck or
PLB_rdDAck is asserted. The throughput of the PLB PIM is measured by using a PLB master to generate a
continuous stream of 16-word or 16-doubleword bursts over a Point-to-Point PLB connection. These bursts are
address-aligned to the size of the burst and include the generation of secondary address requests.
Table 96 describes the maximum throughput of a PLB PIM. The maximum throughput of each PLB PIM is usually
less than the available throughput of the MPMC core. Though each PIM is usually not capable of fully utilizing the
available bandwidth, the remaining MPMC core/NPI bandwidth is available for other ports to use.
For example, a six port MPMC with 64-bit DDR2 memory at 200 MHz is capable of 2226 MB/s of theoretical read
throughput. In that configuration a single PLB PIM is capable of 427 MB/s of throughput. Therefore:
• Four PLB ports, each running at maximum throughput, could achieve a combined system throughput of up to
1708 MB/s (limited by the PLB PIMs).
• Five PLB ports, each running at maximum throughput, could achieve a combined system throughput of up to
2135 MB/s (limited by the PLB PIMs).
• Six PLB ports, each running at maximum throughput, could achieve a combined system throughput of up to
2226 MB/s (limited by the MPMC core).
The PLB PIM throughput is most efficient when the PLB burst address range fits within the MPMC 16-word (32-bit
NPI) and 32-word (64 bit NPI) burst boundaries. MIG PHY Maximum Supported Frequencies by FPGA Family,
page 189 assumes the bursts are aligned to the burst size.
SDMA Latency and Throughput
Device Throughput Estimation for 32-bit NPI Operation
The SDMA is one of several modules in the system; consequently, the throughput numbers reported in this section
are estimates based on the listed assumptions. The overall latency calculations must take into account latency and
throttling because of the individual modules in the system, such as memory, device on LocalLink, and the MPMC.
Table 97 lists the latency results for various operation types.
Table 97: SDMA Latency Expectations
Operation
Latency Between
LocalLink
Clock Cycles
Notes
Rx/Tx
Rx/Tx
Rx/Tx
Tx
Tx
Tx
Tx
Write to Current Description Pointer by PLB
(PAVALID.)
Address Request to NPI Port for first Rx/Tx
Descriptor data (AddrReq)
Address Acknowledge from NPI port (AddrAck.)
Data Available on NPI (NPI RDFIFO Empty
deasserted.)
Data Available on NPI.
Rx/Tx Buffer Descriptor Read Complete.
Rx Buffer Descriptor Read Complete.
Address Request to NPI port for first TX
descriptor data.
Address Acknowledge from NPI port.
Data Available on NPI.
Data Available on NPI.
Tx Buffer Descriptor Read Complete.
Tx Buffer Descriptor Read Complete NPI.
Address Request for first 32-word block burst for
transmission on LocalLink.
17
Z
Memory dependent latency. See MPMC data
sheet for standard values
10
Cacheline Read
10
12 for Read FIFO Port Side Pipeline = 1
Z
Memory-dependent latency. See Table 95,
page 194 for standard values.
10
7
DS643 February 22, 2013
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Product Specification