DS643 Datasheet, PDF (113/216 Pages) Xilinx, Inc – Soft Direct Memory Access (SDMA) support

LogiCORE IP Multi-Port Memory Controller (v6.06.a)
Figure 13 is a block diagram of the MPMC architecture for Spartan-6 FPGAs.
X-Ref Target - Figure 13
PIM0
(Configurable)
MCB
PIM1
(Configurable)
MCB
PIM2
(Configurable)
MCB
PIM3
(Configurable)
MCB
Spartan-6
MCB
Memory
(DDR, LPDDR,
DDR2, DDR3)
PIM4
(Configurable)
MCB
PIM5
(Configurable)
MCB
MPMC
X11196
Figure 13: Spartan-6 FPGA MPMC Architecture
The MPMC is built around the Spartan-6 FPGA MCB so that the MPMC encapsulates the MCB, making it easier to
incorporate into an EDK-based system and providing connectivity and protocol translation using the PIMs.
The MCB supports five basic port configurations that determine the maximum number of ports available, the width
of each port, and if the port has Read-only, Write-only, or bidirectional data flow.
DS643 February 22, 2013
www.xilinx.com
113
Product Specification