DS643 Datasheet, PDF (27/216 Pages) Xilinx, Inc – Soft Direct Memory Access (SDMA) support

LogiCORE IP Multi-Port Memory Controller (v6.06.a)
VFBC PIM I/O Signal
Table 22 lists the VFBC PIM I/O signals.
Table 22: VFBC PIM I/O Signals
Port Name
VFBC Command Interface
VFBC<Port_Num>_Cmd_Clk
VFBC<Port_Num>_Cmd_Idle
VFBC<Port_Num>_Cmd_Reset^(1),(2)
VFBC<Port_Num>_Cmd_Data[31:0]
VFBC<Port_Num>_Cmd_Write
VFBC<Port_Num>_Cmd_End
VFBC<Port_Num>_Cmd_Full
VFBC<Port_Num>_Cmd_Almost_Full
VFBC Write Data Interface
VFBC<Port_Num>_Wd_Clk
VFBC<Port_Num>_Wd_Reset^(1),(2)
VFBC<Port_Num>_Wd_Flush^(1),(2)
VFBC<Port_Num>_Wd_Write
VFBC<Port_Num>_Wd_Data
[C_VFBC<Port_Num>_RDWD_DATA_WIDTH-1:0]
VFBC<Port_Num>_Wd_DataByteEn
[C_VFBC<Port_Num>_WRDWD_DATA_WIDTH/8-1:0]
VFBC<Port_Num>_Wd_End_Burst
Direction
Input
Output
Input
Input
Input
Input
Output
Output
Input
Input
Input
Input
Input
Input
Input
Init
Status
Description
x
Command Clock. Can be asynchronous from the
MPMC_Clk0.
VFBC Idle. Low when the VFBC is actively processing a
1
transfer. High when no transfer is in the VFBC Command
Queue.
x
Command Reset (active-High).
Command Data. (See Required PPC440 Block
x
MI_CONTROL/C_PPC440MC_CONTROL Register
Settings, page 159 for more information on the Command
Packet Data Structure.)
x
Command Write. The command words are pushed onto
the command FIFO when this signal is High.
Command End. When High, the command word currently
being written is the last command word in the command.
x
Used to terminate a command early for non-2D transfers.
Command word 1 is the only valid command word to
provide the End signal.
This signal is usually tied Low.
1
Command FIFO Full. High only when the Command FIFO
is full.
Command FIFO Almost Full. High only when the
1
Command FIFO is almost full. Controlled by the
CMD0_AFULL_CNT parameter.
x
Write Data FIFO Clock. Can be asynchronous from the
MPMC_Clk0.
Write Data FIFO Reset. (active-High)
When asserted, this command:
• Flushes the Write Data FIFO.
• Clears the current Write Command from the
x
Command FIFO.
Resetting the Write Data FIFO returns the internal
read/write FIFO pointers to zero. The current write
command is also removed from the command FIFO even
if the command has not completed.
Write Data FIFO Flush. (active-High)
When asserted this command returns the internal
x
read/write FIFO pointers to zero. Unlike a FIFO reset, the
current write command is kept active in the command
FIFO.
x
Write Data FIFO Push (active-High)
x
Write Data FIFO Data. Must be valid when
VFBC<Port_Num>_Wd_Write is High.
Reserved for Write Data FIFO Byte Enables. This input is
x
currently not used but included for compatibility with future
VFBC PIM versions.
Burst End.
Used only when the transfer is not a multiple of the burst
x
size. If the transfer ends on a non 32-word boundary, this
signal must be asserted High during the last word
transferred.
This signal is usually tied Low for aligned transfers.
DS643 February 22, 2013
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Product Specification