DS643 Datasheet, PDF (97/216 Pages) Xilinx, Inc – Soft Direct Memory Access (SDMA) support

LogiCORE IP Multi-Port Memory Controller (v6.06.a)
MIG provides a GUI in the CORE Generator tool that guides you through the process of generating the pinout and
UCF constraints for their design.
MIG Spartan-3 FPGA PHY Use of Top/Bottom I/O Banks for Data Signals
The MPMC does not support the use of top/bottom memory interface banks for the
Spartan-3/3A/3AN/3E/3A DSP FPGA families. Do not choose top or bottom banks for the DQ or DQS pins of the
memory interface in the MIG tool. You must choose the left or right side banks for the DQ or DQS pins of the
memory interface pinout.
MIG Spartan-3 FPGA Placement of Calibration Control Area Group and BUFG Driving Memory Clock Port MPMC_Clk0
For Spartan-3/3A/3AN/3E/3A DSP FPGA designs, ensure that the system clock input pin is correctly specified to
the MIG tool. This causes the MIG tool to place the tap delay circuit and calibration control (“cal_ctl” area group
near the BUFG corresponding to the top or bottom location of the system clock input pin). The MIG tool does not
allow the use of side BUFGs or DCMs to be directly driving the memory clock. Ensure that in the final design the
“cal_ctl” area group corresponds to the location near the BUFG that drives MPMC_Clk0.
For the correct placement of the calibration control circuit near the BUFG, the UCF uses a device dependent
AREA_GROUP directive with SLICE location calculated by the MIG tool. Verify in FPGA Editor that the “cal_ctl”
area group contains slice locations near the BUFG driving the memory clocks.
In addition to the area group, the UCF contains an RLOC_ORIGIN directive to align a critical section of the tap delay
circuit into a single column inside the “cal_ctl” AREA_GROUP. In MIG v2.3 or later, the AREA_GROUP and
RLOC_ORIGIN values should be calculated automatically.
If an older version of the MIG tool was originally used or if clock circuits have changed, it might be necessary to
re-run the original MIG project files on the current version of MIG. With the standalone mode, constraints missing
from older versions of the MIG tool might need to be corrected. It is also recommended that users verify the correct
placement of BUFG, calibration control, and tap delay circuits as described in the following examples.
Spartan-3 FPGA Top Bank Clock Selection
The MIG output UCF includes an AREA_GROUP constraint on “cal_ctl”. The first value in the RANGE of this
constraint is the value in the RLOC_ORIGIN constraint. Here is an example AREA_GROUP from a MIG output UCF:
AREA_GROUP “cal_ctl” RANGE = SLICE_X74Y190:SLICE_X85Y203;
The first value in the range is X74Y190. This is the RLOC_ORIGIN value and could be missing from MIG v2.2 or
older UCF files. The syntax for the constraint that should be present in the UCF is:
INST “infrastructure_top0/cal_top0/tap_dly0/l0” RLOC_ORIGIN = X74Y190;
Spartan-3 FPGA Bottom Bank Clock Selection
The MIG output UCF includes an AREA_GROUP constraint on “cal_ctl”. To calculate the RLOC_ORIGIN constraint,
take the first value in the AREA_GROUP RANGE and add 10 to the X coordinate. Here is an example AREA_GROUP from
a MIG output UCF:
AREA_GROUP “cal_ctl” RANGE = SLICE_X74Y4:SLICE_X85Y17;
The first value in the range is X74Y4. The new RLOC_ORIGIN value is X84Y4 (because 10 is added to the X
coordinate and could be missing from MIG v2.2 or older UCF files.) The syntax for the constraint that should be
present in the UCF is:
INST “infrastructure_top0/cal_top0/tap_dly0/l0” RLOC_ORIGIN = X84Y4;
Ensure that the “cal_ctl” AREA_GROUP is not located on the left or right sides of the device and that the BUFG
driving the MPMC_Clk0 port is located in the same side of the device near the AREA_GROUP.
DS643 February 22, 2013
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Product Specification