DS643 Datasheet, PDF (33/216 Pages) Xilinx, Inc – Soft Direct Memory Access (SDMA) support

LogiCORE IP Multi-Port Memory Controller (v6.06.a)
Table 27: ECC Register Descriptions (Cont’d)
MPMC_CTRL Base Address +
Offset (hex)
ECC ISC
C_MPMC_CTRL_BASEADDR +0x1C
C_MPMC_CTRL_BASEADDR + 0x20
C_MPMC_CTRL_BASEADDR + 0x24
Register
Name
Access
Default
Type Value (hex)
Description
DGIE⁽¹⁾
IPIS⁽¹⁾
IPIE⁽¹⁾
R/W
R/TOW⁽⁴⁾
R/W
00000000
00000000
00000000
ECC Device Global Interrupt Enable
register.
ECC IP Interrupt Status register.
ECC IP Interrupt Enable register.
Notes:
1. Used when C_INCLUDE_ECC_SUPPORT = 1 only.
2. ROW = Reset On Write. A write operation resets the register.
3. Reset condition of ECCCR depends on the value of parameter C_ECC_DEFAULT_ON.
4. TOW = Toggle On Write. Writing 1 to a bit position within the register causes the corresponding bit position in the register to toggle.
5. RO = Read Only.
6. R/W = Read/Write.
Static PHY Register Summary
Note: This register is available only when the Static PHY is enabled. See Static PHY Interface, page 103 for more information
regarding Static PHY.
Table 28: Static PHY Register Summary
Summary
Grouping
MPMC_CTRL Base Address
+ Offset (hex)
Register Access Default Value
Name
Type
(hex)
Description
Static PHY C_MPMC_CTRL_BASEADDR + 0x1000
SPIR
R/W
Based on
parameter settings
Static PHY Control Register.
MIG PHY Debug Register Summary
The MIG PHY debug registers allow for software-based access into MIG PHY calibration logic, which lets you read
or change the PHY calibration settings. This feature is useful for board bring-up, debug of a memory interface, and
margin analysis. MIG PHY Debug registers are available on Spartan-3, Virtex-4, and Virtex-5 FPGAs only.
These MIG debug registers provide access points into the MIG PHY calibration logic. For more information about
the MIG calibration registers and calibration algorithm, see:
• Memory Interface Solutions User Guides
• XAPP701 (DDR/DDR2 SDRAMs and Virtex-4 FPGAs)
• XAPP768c (DDR SDRAMs and Spartan-3 FPGAs)
• XAPP454 (DDR2 SDRAMs and Spartan-3 FPGAs)
• XAPP851 (DDR SDRAMs and Virtex-5 FPGAs)
• XAPP858 (DDR2 SDRAMs and Virtex-5 FPGAs)
Reference Documents, page 215 contains links to these documents.
To use the MPMC debug registers and to understand the function of these registers, you need to be familiar with
these MIG documents. Also, see the sample software applications located at:
<EDK Install>/sw/XilinxProcessorIPLib/drivers/mpmc_<latest_version>/examples/mpmc_debug*.c.
DS643 February 22, 2013
www.xilinx.com
33
Product Specification