DS643 Datasheet, PDF (103/216 Pages) Xilinx, Inc – Soft Direct Memory Access (SDMA) support

LogiCORE IP Multi-Port Memory Controller (v6.06.a)
You can connect the MPMC_Idelayctrl_Rdy_O to the MPMC_Idelayctrl_Rdy_I of downstream MPMC IP or
other IP blocks. In this situation, explicitly set the C_NUM_IDELAYCTRL and C_IDELAYCTRL_LOC parameters and
follow these instructions even if you are using the integrated MIG GUI flow. If these parameters are explicitly set,
they override the values passed in from the integrated MIG GUI.
The MPMC_Idelayctrl_RDY_0 outputs of upstream IP blocks with IDELAYCTRL can be tied to the
MPMC_Idelayctrl_Rdy_I input.
• Ensure that the MPMC_Idelayctrl_Rdy_I and MPMC_Idelayctrl_Rdy_O ports are not connected in a
circular manner over one or more IP blocks.
• MPMC_Idelayctrl_Rdy_I and MPMC_Idelayctrl_Rdy_O can be left unconnected when not needed. The
EDK XPS tool ties MPMC_Idelayctrl_Rdy_I to high automatically when it is unconnected.
Additional MIG Information
Answer Records, Application Notes, and the Memory Interface Solutions User Guide provide important information
about the Spartan-3, Virtex-4, Virtex-5, and Virtex-6 FPGA MIG PHY, the MIG UCF constraints, and board layout
guidelines. These resources help to debug and bring up MPMC designs using the MIG PHY:
• The Xilinx memory page contains the Memory Interface Solutions User Guide and other relevant content.
• Answer Records contain useful design, debug, and implementation content.
• Application notes describe the operational theory and implementation of the underlying MIG PHYs.
Reference Documents, page 215 contains links to these resources.
Static PHY Interface
Static PHY contains the following topics:
• Static PHY Features
• Static PHY Implementation
• Static PHY Implementation Considerations
• Static PHY Interface Register
• Example Static PHY Calibration Algorithm
Static PHY Features
The Static PHY interface available in Spartan-3, Virtex-4, and Virtex-5 FPGA designs and the MPMC is based on
DCM phase adjustment. This PHY is used for SDRAM. For DDR/DDR2, it can also be used in cases when a
MIG-based PHY is not available or cannot be used.
The MPMC Static PHY interface is an alternative to the Memory Interface Generator (MIG)-based PHY interface.
The Static PHY uses DCM-based fine phase adjustments to generate a read data capture clock instead of using
IDELAYs or LUT-based delays to shift the input read data.
Note: Xilinx recommends that you design for, and use, a MIG-based PHY whenever possible for best results. MIG-based PHY
interfaces offer greater timing margin, are more robust, and use fewer global clock buffer resources; the Static PHY is available
when MIG-based PHY is not an option.
As an example, the Static PHY might be used when a legacy board that was designed for a different memory controller and does
not use a MIG-compatible pinout. All new designs should target the use of the MIG-based PHY.
DS643 February 22, 2013
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Product Specification