DS643 Datasheet, PDF (134/216 Pages) Xilinx, Inc – Soft Direct Memory Access (SDMA) support

LogiCORE IP Multi-Port Memory Controller (v6.06.a)
For Transmit channels, STS_CTRL_APP0.Completed=1 indicates to the software application that the data in the
associated buffer has been transmitted and is free to be modified.
If an error occurs during the DMA transfer, either during the descriptor fetch and update or during the actual
requested DMA transfer, the STS_CTRL_APP0.Error bit is set.
If an error occurs during a transfer, an IRQ_REG.ErrIrq interrupt is generated, the respective
CHNL_STATUS.EngBusy is cleared to 0, and DMA operations are halted. Now the Software application must issue
a reset to the SDMA to reset and resume DMA operations by writing a 1 to the DMA_CONTROL.SwReset bit.
Dynamic Descriptors
At times it might be necessary to update a descriptor chain while the SDMA is actively processing the buffer
descriptors. This can be achieved when a channel is configured to operate in TailPointer mode.
Appending a Descriptor Chain
The SDMA is designed so software applications can append new buffer descriptor chains into an already active
chain with minimal effort on the part of the software application.
This can be accomplished by updating the TAILDESC_PTR if the descriptors are arranged in a ring. This method is
as follows:
If no updates were made to the descriptor chain, the DMA controller would process Descriptor 0 through
Descriptor 9 and stop after Descriptor 9 because the original TAILDESC_PTR would equal the CURDESC_PTR of
Descriptor 9.
For this example, assume that the software application has started DMA operation by setting the TAILDESC_PTR
address to Descriptor 9. The SDMA fetches and begins processing Descriptor 0. Now the software determines that
it is necessary to append Descriptors 10, 11, and 12 to the already active chain.
To append the new descriptors:
1. Set up Descriptors 10, 11, and 12 in remote memory.
2. Update the NXTDESC_PTR of the descriptor in memory space to point to descriptor.
3. Update the TAILDESC_PTR register with the address of Descriptor 12.
If the SDMA is in the middle of processing Descriptor 9, a race condition occurs. The NXTDESC_PTR that SDMA
picks up is pointing to a potentially invalid location.
If the software application updates NXTDESC_PTR in memory space and then updates the TAILDESC_PTR in the
SDMA, the SDMA does not update its NXTDESC_PTR register from memory space and, consequently fetches the
next descriptor from an invalid place.
Modifying a Descriptor Using A Descriptor Ring
When using a descriptor ring to modify a descriptor, no new descriptors are added. Consider a situation where 14
descriptors are arranged in a loop and the stop point from Descriptor 13 must be moved to Descriptor 5 without
stopping the chain. It is assumed that the new descriptor chain was created in remote memory and that the SDMA
is actively processing the original descriptor chain. To perform that operation:
1. Modify the already processed descriptors, such as the descriptor with the field setting
STS_CTRL_APP0.Completed = 1.
2. Move TAILDESC_PTR to point at Descriptor 5.
DS643 February 22, 2013
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Product Specification