DS643 Datasheet, PDF (204/216 Pages) Xilinx, Inc – Soft Direct Memory Access (SDMA) support

LogiCORE IP Multi-Port Memory Controller (v6.06.a)
Table 99: Read and Write Port Block RAM Usage (Spartan-3, Virtex-4, and Virtex-5 FPGAs) (Cont’d)
0 block RAMs if read-only port (C_PI<Port_Num>_WR_FIFO_TYPE = DISABLED) or for IXCL/IPLB PIM subtypes.
1 block RAM for 32-bit NPI port width and 8/16-bit DDR/DDR2 memory.
1 block RAM for 32-bit NPI port width and 8/16/32-bit SDRAM.
Write Ports _{2 block RAMs for 64-bit NPI port width or 32-bit DDR/DDR2 memory or 64-bit SDRAM.}
On Virtex-5 FPGAs, there is an optimization where 1 block RAM is used for 64-bit NPI with 32-bit DDR/DDR2 or 64-bit
SDRAM.
4 block RAMs for 64-bit DDR/DDR2 memory.
1. NPI Width is defined as: SDMA = 64 bits, XCL = 32 bits PLB PIM = value of parameter C_SPLB<Port_Num>_NATIVE_DWIDTH (the default is 64 and
this value must be 64 for IPLB and DPLB SUBTYPES), NPI = value of parameter C_PIM<Port_Num>_DATA_WIDTH (default is 64).
Table 100 shows the block RAM usage for each Read and Write port for the Virtex-6 device.
Table 100: Read and Write Port Block RAM Usage (Virtex-6 FPGAs)
0 block RAMs if write-only port (C_PI<Port_Num>_RD_FIFO_TYPE = DISABLED).
1 block RAM for 32-bit NPI⁽¹⁾ port width and 8-bit DDR2/DDR3 memory.
2 block RAMs for 64-bit NPI port width or 32-bit DDR2/DDR3 memory or 64-bit SDRAM.
Read Ports
1 block RAM for 64-bit NPI⁽¹⁾ port width and 16-bit DDR2/DDR3 memory.
2 block RAMs for 32-bit NPI⁽¹⁾ port width and 16-bit DDR2/DDR3 memory.
4 block RAMs for 64-bit DDR2/DDR3 memory.
0 block RAMs if read-only port (C_PI<Port_Num>_WR_FIFO_TYPE = DISABLED) or for IXCL PIM subtypes.
1 block RAM for 32-bit NPI⁽¹⁾ port width and 8-bit DDR2/DDR3 memory.
Write Ports
2 block RAMs for 64-bit NPI⁽¹⁾ port width and 8-bit DDR2/DDR3 memory.
1 block RAMs for 64-bit NPI⁽¹⁾ port width and 16-bit DDR/DDR3 memory.
2 block RAMs for 32-bit NPI⁽¹⁾ port width and 16-bit DDR/DDR3 memory.
4 block RAMs for 32-bit DDR2/DDR3 memory.
1. NPI Width is defined as: SDMA = 64 bits, XCL = 32 bits PLB PIM = value of parameter C_SPLB<Port_Num>_NATIVE_DWIDTH (the default is 64 and
this value must be 64 for IPLB and DPLB SUBTYPES), NPI = value of parameter C_PIM<Port_Num>_DATA_WIDTH (default is 64).
To conserve block RAMs, the MPMC can be configured to use SRL FIFOs instead of block RAM FIFOs. With a 64-bit
NPI:
• Each read SRL FIFO uses approximately 288 LUTs per port.
• Each write SRL FIFO uses approximately 256 LUTs per port.
The use of SRL FIFOs might negatively impact timing due to the slower speed of SRL FIFOs compared to block
RAMs.
The VFBC PIM uses several RAMs depending on the FIFO sizes. See VFBC PIM Slice, LUT, FF, Slice, and Block
RAM Resource Utilization, page 208.
Note: Spartan-6 FPGAs do not use block RAMs with the exception of VFBC PIMs or Performance Monitors.
Resource (LUT, Flip-Flop, and Slice) Utilization
This section provides estimates for Lookup Table (LUT), Flip-Flop (FF), and Slice utilization for the MPMC and
PIMs. The values provided are for resource estimation and are not guaranteed. These estimates assume default
MPMC settings and default implementation tool options. Actual FPGA resource utilization depends on exact
MPMC configuration parameters and implementation tool optimizations including cross boundary logic
optimization, logic sharing, register re-timing, global system optimization, logic trimming, timing targets, and
implementation tool settings.
DS643 February 22, 2013
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