DS643 Datasheet, PDF (95/216 Pages) Xilinx, Inc – Soft Direct Memory Access (SDMA) support

LogiCORE IP Multi-Port Memory Controller (v6.06.a)
The MMCM location constraints must be transferred to the UCF of the MPMC design.
See Virtex-6 FPGA Clock Logic, page 60 for more information about clocking requirements.
Standalone Flow: Migrating an MPMCv3 Design to MPMCv5
If using the Virtex-4 FPGA DDR or DDR2 MIG PHY or the Virtex-5 FPGA DDR PHY, no revision (revup) is
required. A revup is required for Spartan-3 FPGA DDR/DDR2 and Virtex-5 FPGA DDR2 MIG PHY designs. You
can run MIG and use the MIG > Update Design option to open the MIG v1.73 project file and generate a new
constraint file. Using MIG to update the constraint file is the strongly recommended flow.
For cases where the MIG > Update Design flow is not possible, the following script is provided to revup an MPMC
v3.00.a or v3.00.b design that uses a MIG v1.73 PHY to an MPMC v5 design that uses a MIG PHY.
• To revise a Spartan-3/3A/3AN/3E/3A DSP FPGA DDR or DDR2 design where the MIG > Update Design
flow is not practical, execute the following commands in a shell where ISE tools are in the path:
cd <EDK_Install_Dir>/hw/XilinxProcessorIPLib/pcores/mpmc_<version>/data
xilperl revup_s3_ucf.pl <MPMC v3 UCF> <USER UCF>
where:
- <EDK_Install_Dir> is the directory in which the EDK is installed.
- <MPMC v3 UCF> is the name of your UCF from your mpmc_v3_00_a or mpmc_v3_00_b project.
- <USER UCF> is the UCF to be used in your MPMC project. Delete any constraints containing “RLOC_ORIGIN”
statements because these are no longer applicable.
To revise a Virtex-5 FPGA DDR2 design from MPMCv3 to MPMCv5, a MIG > Update Design flow must be
followed. The steps are:
1. A MIG project must be generated, if not already existing, using either the integrated or standalone MIG flow.
Note: Because a pinout is already available, all banks can be selected in the bank selection screen.
2. If the default MIG pinout generated is not the desired pinout, run the MIG > Update Design flow using the
MIG project, and a UCF with the desired pinout in a MIG-formatted UCF.
Note: The input UCF parsing to the MIG > Update Design flow currently requires strict adherence to the formatting similar
to MIG UCF output for complete Update Design UCF parsing.
Warnings in this step relating to missing pins in the UCF can be ignored if similar pins are not used by MPMC.
For example the clk200_p, clk200_n, sys_rst_n, phy_init_done, and extra ddr2_cs_n, ddr2_odt,
ddr2_ck, and ddr_ck_n ports can be ignored during this step.
3. If using the standalone MIG flow, convert the MIG UCF to MPMC and include into the system UCF by
completing the steps in Standalone Flow: Converting a MIG UCF to an MPMC UCF, page 94. This step can be
skipped when using the integrated MIG flow because MPMC converts and manages the final UCF.
More information on the MIG Update Design flow can be found in the MIG documentation. Reference Documents,
page 215 contains a link to that documentation.
Standalone Flow: Migrating an MPMCv4 Virtex-5 FPGA DDR2 Design to MPMCv5
To migrate an existing Virtex-5 FPGA DDR2 design from MPMCv4 to MPMCv5, the following actions are
necessary. All other MIG PHY types do not need special consideration to be revised.
Note: Tool errors are reported if these steps are not performed.
• In the MHS file, the C_MEM_DQS_IO_COL and C_MEM_DQ_IO_MS parameters are no longer used and must be
removed.
• In the UCF, MPMC specific constraints containing AREA_GROUP and RLOC_ORIGIN must be removed.
DS643 February 22, 2013
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