DS643 Datasheet, PDF (188/216 Pages) Xilinx, Inc – Soft Direct Memory Access (SDMA) support

LogiCORE IP Multi-Port Memory Controller (v6.06.a)
Performance, Timing, and Resource Utilization
The following subsections describe:
• MPMC Operational Frequencies
• MPMC Optimization
• MPMC Latency and Throughput
• Resource Utilization
MPMC Operational Frequencies
This subsection contains:
• Operating Frequency Range by Device
• MIG PHY Supported Fmax
Operating Frequency Range by Device
Table 93 lists the target operating frequency range for the MPMC for many device families and speed grades. These
values provide guideline MPMC_Clk0 frequencies for the MPMC. Generally:
• The XCL, PLB, and SDMA PIMs can run 1:1 or 1:2 clock ratio to MPMC_Clk0.
• A 1:1 clock ratio is most common for SDRAM and Spartan-6 FPGA designs.
• A 1:2 clock ratio is most common with DDR/DDR2/DDR3 designs on Spartan-3, Virtex-4, Virtex-5, and
Virtex-6 FPGAs.
Table 93: Target Operating Frequency Ranges by FPGA Family
FPGA Family
Target Fmax Range (MHz)
Spartan-3 Generation, -4 Speed Grade
125-133
Spartan-3 Generation, -5 Speed Grade
133-166
Virtex-4, -10 Speed Grade
165-185
Virtex-4, -11 Speed Grade
185-205
Virtex-4, -12 Speed Grade
200-225
Virtex-5, -1 Speed Grade
175-200
Virtex-5, -2 Speed Grade
185-220
Virtex-5, -3 Speed Grade
210-250
Virtex-6 -1 Speed Grade
175-200
Spartan-6 -2 Speed Grade
80-90
The values shown in Table 93 are based on the following condition assumptions (unless noted):
• Default parameters settings for the MPMC
• 1:2 PIM to MPMC_Clk0 clock ratios
• No use of floorplanning
• Default implementation tool options
Note: The target Fmax is influenced by the exact system and is provided for guidance. It is not a guaranteed value across all
systems. The Fmax timing for the MPMC Performance Monitors has not been characterized and could be significantly lower. The
Fmax timing for SDRAM has not been characterized and is likely to be limited by the physical system.
DS643 February 22, 2013
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Product Specification