DS643 Datasheet, PDF (94/216 Pages) Xilinx, Inc – Soft Direct Memory Access (SDMA) support

LogiCORE IP Multi-Port Memory Controller (v6.06.a)
8. Run the convert_ucf.pl script as outlined in Standalone Flow: Converting a MIG UCF to an MPMC UCF,
page 94 to convert the MIG UCF to an MPMC UCF, then copy the UCF information into the
<EDK_Project>/data/system.ucf.
9. Update the UCF to include the correct port names for your design.
For example, the convert_ucf script produces port names like fpga_0_DDR_SDRAM_DDR_DQ and
fpga_0_DDR_SDRAM_DDR_Addr_pin similar the BSB port naming. Those MPMC UCF port names should be
updated to reflect the actual top-level port names in the system.mhs file.
10. Ensure that the MPMC core is configured for the correct memory part and memory configuration in XPS using
the MPMC GUI. The MPMC core memory parameters must match the settings in the MIG GUI for the UCF
constraints to match the logic that is generated.
11. Retain the MIG project file with the MPMC project files. The original MIG project file might be needed to
modify the design, revise to a newer version of MPMC, or for debug and testing.
Note: The UCF provided with BSB-generated designs might not match the format and values provided by the MIG UCF
conversion script when using Xilinx and third-party boards that do not have an exact MIG-generated pinout. In many cases these
UCF files are manually generated and maintained.
Standalone Flow: Converting a MIG UCF to an MPMC UCF
In the Standalone MIG GUI Flow, you must run a script to modify the MIG-generated UCF to be compatible with
the MPMC design. This involves changing the instance and internal path names of the constraints to match MPMC.
Note: This manual UCF conversion step is not required when the Integrated MIG GUI Flow is used.
A script is provided at:
<EDK_Install_Dir>/hw/XilinxProcessorIPLib/pcores/mpmc_<version>/data/convert_ucf.pl to assist
with the process of converting a MIG UCF into an MPMC UCF.
After running the MIG tool to generate a Verilog MIG design, take the UCF from the
/mig_<version>/user_design/par directory and execute this script in a shell where ISE and EDK tools are in
the path environment:
xilperl <EDK InstallDir>
/hw/XilinxProcessorIPLib/pcores/mpmc_<version>/data/convert_ucf.pl
--family [device family] [--mhs <MHS File>] <MIG UCF> <OUTPUT UCF>
The --family option should specify either the spartan3, virtex4, virtex5 or virtex6 device family of the design.The
optional --mhs flag with the entire system <MHS File> provided as an argument uses the MHS net names for the
memory signals in <OUTPUT_UCF>. You must add the contents of the <OUTPUT UCF> file into the user EDK project
UCF manually, such as <EDK_Project_Dir>/data/system.ucf.
This script is provided to assist with the process of translating the UCF but it does not necessarily generate a
complete working UCF to use with the MPMC. You must still verify the output of the script and you might need to
adjust it to fit a particular design. Unless the --mhs option is used, the script does not completely translate the
names of clock, reset, or memory I/O signals to match the top level port names in the EDK design. You must
translate these signal names to match your design.
In Virtex-6 FPGA designs, you must:
• Open the generated MIG files and obtain the values needed to set MPMC parameters C_MEM_NDQS_COL0,
C_MEM_NDQS_COL1, C_MEM_DQS_LOC_COL0, and C_MEM_DQS_LOC_COL1. These parameters are located in the
<MIG_project>/user_design/rtl/ip_top directory in the top-level file of your design name. The MIG
parameter names do not have the C_MEM_ prefix.
• In the UCF, use LOC on the MMCM used with MPMC in the same location as specified by MIG.
The MIG tool specifies the location of the MMCM external to MPMC that drives the MPMC signals
MPMC_Clk_Rd_Base, and MPMC_Clk_Mem.
DS643 February 22, 2013
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Product Specification