DS643 Datasheet, PDF (107/216 Pages) Xilinx, Inc – Soft Direct Memory Access (SDMA) support

LogiCORE IP Multi-Port Memory Controller (v6.06.a)
Matching Delay Traces
Because the Static PHY uses a DCM to capture the Read data, ensure that boards designed to use the Static PHY
have matched delay traces across all data lanes. This reduces the skew across the data bits and improves timing
margin. Place data pins in the same bank or in adjacent banks to further reduce skew across data bits (clock module
skew in the FPGA is smaller if pins are placed together).
Static PHY Interface Register
You can configure the Static PHY interface statically by using the following parameters to set the start-up values for
the signals that control the Static PHY:
• C_STATIC_PHY_RDDATA_CLK_SEL
• C_STATIC_PHY_RDDATA_SWAP_RISE
• C_STATIC_PHY_RDEN_DELAY
You can then change these values dynamically by using the PLB Control register. Additionally, you can change the
phase delay of a DCM that generates MPMC_Clk_Mem using the PLB Control register.
DS643 February 22, 2013
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Product Specification