DS643 Datasheet, PDF (109/216 Pages) Xilinx, Inc – Soft Direct Memory Access (SDMA) support

LogiCORE IP Multi-Port Memory Controller (v6.06.a)
Example Static PHY Calibration Algorithm
The following steps provide how to use the Static PHY Interface PLB control register to calibrate the PHY interface
automatically. The software must be run before any other writes or reads are sent to the MPMC. Additionally, the
software instructions must be stored in block RAM until the MPMC memory is calibrated.
1. Wait for INIT_DONE bit to be set.
2. Ensure DCM_TAP_VALUE equals the initial DCM phase shift setting. If it is not equal, stop here, report error, and
rebuild hardware with DCM phase shift set to 0.
3. Set RDDATA_CLK_SEL to 0.
4. Set RDDATA_SWAP_RISE to 0 (DDR and DDR2 only.)
5. Set RDEN_DELAY to the minimum value, typically 0. (This can cause a processor hang if you are not using port
0 for calibration reads. If this is the case, you might need to increase the minimum start value and maximum
end value for this parameter. See "Static PHY Implementation," for more details.)
6. Set the DCM phase shift to the minimum value using DCM_PSEN, DCM_PSINCDEC, and DCM_DONE.
7. Write and verify pattern in memory without data cache. If there is a mismatch, clear the valid count, and skip
to step 11.
Note: Using a large pattern that introduces a large amount of data bus toggling might improve calibration results, but also
increases calibration time. The data written to memory for the calibration pattern should ensure a high amount of data bit
toggling for the memory width being used. For example, writing 0x00000000 followed by 0xFFFFFFFF successively
toggles all bits for a 32-bit memory but does not cause as many data bit transitions on an 8- or 16-bit memory.
8. Enable the data cache.
9. Read the pattern back and verify. Flush and invalidate the data cache. If there is a mismatch, clear the valid
count and back to step 8.
10. Increase the DCM phase shift, keeping track of how many patterns were read back correctly.
11. Repeat steps 8 through 10 until maximum phase shift value is reached. Do not proceed beyond this step until a
match is found.
12. If the number of correctly read patterns in a row is greater than an acceptable threshold, set DCM phase to
midpoint of largest found acceptable range.
13. Increase RDEN_DELAY by 1 and repeat steps 6 through 13 until maximum RDEN_DELAY.
14. Set RDDATA_SWAP_RISE to 1. Repeat steps 5 through 14 (DDR and DDR2 only.).
15. Set RDDATA_CLK_SEL to 1. Repeat steps 4 through 15.
16. If this step is reached, calibration was not possible. Stop and report error. Your settings are saved until you
power down your board, even with an MPMC system reset. Ensure that a system reset does not force your
DCM phase shift setting to revert back to the initial value. If this is the case, you need to modify your reset
structure, rebuild your hardware, and re-run the calibration.
Note: You might want to build a simple single port MPMC system with a Static PHY, use a software program to characterize the
ideal set of static PHY settings for that board, then initialize those settings into the design or reduce the search range of your
calibration program.
DS643 February 22, 2013
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