DS643 Datasheet, PDF (147/216 Pages) Xilinx, Inc – Soft Direct Memory Access (SDMA) support

LogiCORE IP Multi-Port Memory Controller (v6.06.a)
SDMA Receive Data Write
Figure 30 shows received data being written to the MPMC. The SDMA uses 32-word burst writes to write data to
MPMC. The transfers are always 32-word aligned. The PI_WrFIFO_BE bus is used to indicate which bytes of the 32
words are valid. The first two bytes are shown as being invalid and the last byte is also invalid.
X-Ref Target - Figure 30
0ns
PI_CIk
PI_Addr[31:0]
PI_AddrReq
PI_RNW
PI_AddrAck
PI_Size[3:0]
50ns
100ns
150ns
200ns
250ns
300ns
A0
4
PI_RdFIFO_Data[63:0]
PI_RdFIFO_Pop
PI_RdFIFO_RdWdAdd[3:0]
PI_RdFIFO_DataAvailable
PI_RdFIFO_Empty
PI_RdFIFO_Flush
PI_WrFIFO_Data[63:0]
PI_WrFIFO_BE[7:0]
PI_WrFIFO_Push
PI_WrFIFO_AlmostFull
PI_WrFIFO_Flush
D0 D1 D2
D3
D4
D5 D6
D7 D8
D9 D10 D11 D12 D13 D14 D15
3F FF FF FF
FF FF FF FF FF FF FF FF FF FF
FF FE
Figure 30: Receive Data Write
DS607_24_030408
SDMA Transmit LocalLink
Figure 31 shows an example transmit LocalLink transfer of 8 words.
Note: During a transmit the first buffer descriptor is transferred in the header of the LocalLink data stream.
X-Ref Target - Figure 31
0ns
LLink_Clk
TX_D[31:0]
TX_REM[3:0]
TX_SOF
TX_SOP
TX_EOP
TX_EOF
TX_Src_Rdy
TX_Dst_Rdy
50ns
100ns
150ns
200ns
Hdr0
Hdr1 Hdr2 Hdr3 Hdr4 Hdr5 Hdr6 Hdr7 D0 D1 D2 D3 D4 D5 D6 D7
'b0000
RX_D[31:0]
RX_REM[3:0]
RX_SOF
RX_SOP
RX_EOP
RX_EOF
RX_Src_Rdy
RX_Dst_Rdy
Figure 31: Transmit LocalLink Timing
DS643_32_071307
DS643 February 22, 2013
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Product Specification