DS643 Datasheet, PDF (101/216 Pages) Xilinx, Inc – Soft Direct Memory Access (SDMA) support

LogiCORE IP Multi-Port Memory Controller (v6.06.a)
Do not copy the pinout of evaluation boards that do not match a supported MIG-generated pinout. User boards
must be designed exactly to the pinout provided by the prescribed version of MIG. Non-MIG pinouts might not be
supported and might not be robust. User boards must also follow all layout recommendations specified in the
Memory Interface Solutions User Guide, including special trace delays for the DQS_DIV_O to DQS_DIV_I loopback
signal (Spartan-3 FPGA PHY). Reference Documents, page 215 contains a link to this document.
It is highly recommended that if you are developing a new custom board, run the MIG design with hardware test
bench logic or an MPMC test design through the full ISE tool flow to verify that proposed pinouts implement
properly through the ISE tools.
Tips and Hints for Board Bring Up
The following are tips and hints that can be useful during board bring up:
• During initial bring-up of the MPMC on a new board, Xilinx recommends that you start with a single-port
MPMC with PLB PIM. This design should be modeled off a simple BSB-based MicroBlaze processor design
with caches disabled.
• During initial bring-up, start running the memory controller at the minimum clock speed that the memory
device supports to establish as a working baseline. Then increase the memory clock speed up to the desired
frequency.
• Use the MicroBlaze processor with a Single-Port MPMC design and connect with the XMD. Then perform
simple reads and writes to establish whether basic memory transactions work.
• Incrementally add complexity to the design by building it up to be closer to your desired MPMC system
configurations. For example, after getting the single-port design to work, enable MicroBlaze processor caches
and connect the MicroBlaze processor IXCL/DXCL ports to a three Port XXP MPMC design (2 XCL + 1 PLB).
Establish that memory transactions continue to work with caches off and try the test with caches on to test
burst read transactions from memory.
• Run the MPMC extended memory test application located at
<EDK_Directory>/sw/XilinxProcessorIPLib/drivers/mpmc_<latestversion>
/examples/mpmc_mem_test_example.c.
• Make use of the MPMC Debug register functionality described on MIG PHY Debug Register Summary These
debug registers allow you to read or set the MIG PHY calibration settings manually through a processor
accessible interface.
• Use default MPMC settings wherever possible. Customize or optimize the design parameters after you have a
working baseline system.
• Check the PAR report to ensure all memory I/Os are “LOCed”. Ensure that map is run with the -pr b option
to ensure IOB flip-flop packing.
• Try running a standalone MIG controller design. The MIG tool can produce an example standalone loopback
design that can be useful for debugging physical level MIG PHY problems.
• Check that the maximum clock frequency limitations of the underlying MIG PHY are not exceeded. See MIG
PHY Supported Fmax for more information.
• Do not use a clock frequency lower than the minimum operating frequency of the memory device. For
example some DDR2 devices have a minimum clock frequency specification of 125 MHz.
• For Dual Rank or Dual DIMM designs, note the warnings that such designs are strongly discouraged. If a Dual
Rank or Dual DIMM design is still used, try to establish a working baseline system accessing only one of the
ranks of memory.
DS643 February 22, 2013
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