DS643 Datasheet, PDF (31/216 Pages) Xilinx, Inc – Soft Direct Memory Access (SDMA) support

LogiCORE IP Multi-Port Memory Controller (v6.06.a)
Table 24: MPMC Dependencies (Cont’d)
Parameter Name
Affects Signal
C_MEM_DM_WIDTH
C_ECC_DM_WIDTH
DDR3_DM
DDR2_DM
DDR_DM
SDRAM_DM
C_MEM_DQS_WIDTH
C_ECC_DQS_WIDTH
DDR3_DQS
DDR3_DQS_n
DDR2_DQS
DDR2_DQS_n
DDR_DQS
C_MEM_ODT_WIDTH
DDR3_ODT
DDR2_ODT
C_NUM_PORTS
PIM<Port_Num>_*
C_INCLUDE_ECC_SUPPORT
MPMC_ECC_Intr
C_FAMILY
rzq
C_MEM_CALIBRATION_SOFT_IP
zio
Relationship Description
Width of data mask bits at memory interface.
Width of data strobe bits at memory interface.
Width of ODT bits to memory.
Determines number of ports attached to MPMC.
Interrupt output available only if
C_INCLUDE_ECC_SUPPORT = 1.
When C_MEM_CALIBRATION_SOFT_IP = TRUE and
device family is Spartan-6, rzq and zio I/O pins are
actively used.
PLB v4.6 Bus Parameter and I/O Signal Dependencies
Table 25 lists the parameter and I/O signal dependencies for the slave PLB PIM, as well as for the slave PLB control
interfaces on the SDMA and MPMC. The slave PLB bus names on the SDMA and MPMC are SDMA_CTRL and
MPMC_CTRL, respectively. See the I/O Signals, page 16 for parameter prefix options.
Table 25: PLB v4.6 PIM Dependencies
Parameter
Affects
Relationship Description
C_SPLB<Port_Num>_SUPPORT_BURSTS C_PIM<Port_Num>_SUBTYPE
C_PIM<m>_SUBTYPE must be set to PLB
when
C_SPLB<Port_Num>_SUPPORT_BURSTS =1
if the desired PIM must support single, cache
line, and burst transactions.
C_PIM<Port_Num>_SUBTYPE must be set to
PLB when
C_SPLB<Port_Num>_SUPPORT_BURSTS = 0
if the desired PIM must support single
transactions only.
C_SPLB<Port_Num>_SMALLEST_MASTER C_SPLB<Port_Num>_NATIVE_DWIDTH
See Supported PLB Master and Bus Widths,
page 156.
C_PIM<Port_Num>_SUBTYPE
C_SPLB<Port_Num>_SUPPORT_BURSTS
C_SPLB<Port_Num>_SUPPORT_BURSTS
must be set to1 when
C_PIM<Port_Num>_SUBTYPE = PLB for the
PIM to support single, cache line, and burst
transactions.
C_SPLB<Port_Num>_SUPPORT_BURSTS
must be set to 0 when
C_PIM<Port_Num>_SUBTYPE = PLB for the
PIM to support single transactions only.
C_SPLB<Port_Num>_NATIVE_DWIDTH
When C_PIM<Port_Num>_SUBTYPE = PLB,
C_SPLB<Port_Num>_NATIVE_DWIDTH can
be 32 or 64.
When C_PIM<Port_Num>_SUBTYPE =
DPLB or IPLB,
C_SPLB<Port_Num>_NATIVE_DWIDTH must
be set to 64.
C_PIM<Port_Num>_OFFSET
SPLB<Bus_Name>_PLB_ABus
Access to memory is at address the of
SPLB<Port_Num>_ABus plus
C_PIM<Port_Num>_OFFSET.
Dependencies Applying to all Slave I/O Signals
DS643 February 22, 2013
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Product Specification