DS643 Datasheet, PDF (3/216 Pages) Xilinx, Inc – Soft Direct Memory Access (SDMA) support

LogiCORE IP Multi-Port Memory Controller (v6.06.a)
The LogiCORE IP Facts table on page 1 lists the supported device families for the MPMC. The MPMC also supports
derivative architectures as listed in www.xilinx.com/ise/embedded/ddsupport.htm; however, consult MIG
documentation for latest device and derivative device support information. The MPMC generally treats derivative
device families such as Automotive (XA), Aerospace and Defense (Q, QR, XQ), and Low Power (L) as the
equivalent base family device.
Note: MPMC and MIG designs might not have been retested or recharacterized across all derivative device families in
hardware.
Design Parameters
Table 2 through Table 10 provide the design parameters, allowable values, and descriptions for the MPMC system,
associated memory, and Personality Interface Modules (PIMs). Parameter values that are strings or that contain
alphanumeric characters must be upper case.
System Parameters
Table 2 lists the system parameters.
Table 2: System Parameters
Parameter Name
C_ALL_PIMS_SHARE_ADDRESSES⁽¹⁾
C_ARB_PIPELINE⁽⁷⁾
C_ARB_USE_DEFAULT
C_ARB0_ALGO
C_ARB0_NUM_SLOTS
C_ARB0_SLOT0
.
.
.
C_ARB0_SLOT15
C_DEBUG_REG_ENABLE
Default
Value
1
1
0
ROUND_ROBIN
1
NONE
0
Allowable
Values
Description
Specifies whether MPMC ports use the
C_MPMC_BASEADDR and C_MPMC_HIGHADDR for
address decoding or if ports have independent
address range decoding. Also specifies whether
SDMA control register interfaces use the
C_SDMA_CTRL_BASEADDR and
C_SDMA_CTRL_HIGHADDR for address decoding or
0,1
MPMC ports and SDMA control register ports have
independent address range decoding.
1 = MPMC ports use C_MPMC_BASEADDR and
C_MPMC_HIGHADDR for address decoding; SDMA
control registers use C_SDMA_CTRL_BASEADDR
and C_SDMA_CTRL_HIGHADDR.
0 = MPMC ports and SDMA control registers have
independent address range decoding.
Enables or disables the Arbiter Pipeline:
0,1
0 = Disable Arbiter Pipeline.
1 = Enable Arbiter Pipeline. (performance)
0
Default Arbitration Algorithm to use
(unimplemented).
ROUND_ROBIN,
FIXED, CUSTOM
String that specifies the arbitration scheme to use
for Algorithm 0 (Custom will consume a block RAM).
Only valid if C_NUM_PORTS > 1. When set to FIXED,
the priority order is from Port 0 to Port 7 and cannot
be changed irrespective of C_ARB0_SLOTx
settings.
1-16
Number of time slots to use for Custom Algorithm.
Only valid if C_ARBO_ALGO = CUSTOM.Can only
be set to 10 or 12 on Spartan-6 FPGAs.
String of Numbers
Example:
“01234567”
Arbitration Priority for Time Slot n where n is
0-15, and the number of valid Time Slots is from 0
to (C_ARB0_NUM_SLOTS-1).
Left to right, highest to lowest priority. Every valid
port must be specified once only.
Only valid if C_ARBO_ALGO = CUSTOM.
0 = Disable MIG Debug registers
0,1
1 = Enable MIG Debug registers
(Spartan-3, Virtex-4, and Virtex-5 FPGA MIG PHY
only).
DS643 February 22, 2013
www.xilinx.com
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Product Specification