DS643 Datasheet, PDF (106/216 Pages) Xilinx, Inc – Soft Direct Memory Access (SDMA) support

LogiCORE IP Multi-Port Memory Controller (v6.06.a)
NET <MPMC_instance_name>/*rd_data_rise_in* MAXDELAY = <half_clock_period>; #DDR/DDR2
NET <MPMC_instance_name>/*rd_data_fall_in* MAXDELAY = <half_clock_period>; #DDR/DDR2
NET <MPMC_instance_name>/*rd_data_rise_rdclk* MAXDELAY = <half_clock_period>; # SDRAM
If you plan to adjust the DCM phase settings dynamically to locate an optimal DCM clock phase shift, it is
recommended to tighten the timing constraint so there is more margin to account for the potential MPMC_Clk_Mem
phase shift range:
NET <MPMC_instance_name>/*rd_data_rise_in* MAXDELAY = 1000 ps; #DDR/DDR2
NET <MPMC_instance_name>/*rd_data_fall_in* MAXDELAY = 1000 ps; #DDR/DDR2
NET <MPMC_instance_name>/*rd_data_rise_rdclk* MAXDELAY = 1000 ps; # SDRAM
Note: Ensure that the map is run with the option -pr b set to ensure that the tools pack internal flip-flops into the IOBs. You
might also need to relax the maxdelay value from the preceding examples to meet timing depending on the speed of the FPGA.
DCM Phase Adjust Port
The MPMC DCM phase adjust control port lets you increase and decrease the phase adjustment value of the DCM.
The phase adjustment that the MPMC performs is relative to the initial phase value set in the DCM. You must
instantiate the DCM itself outside of the MPMC.
You must configure the DCM in the proper operating mode with the necessary parameters set for your system.
The MPMC provides the control signals to generate commands to change the phase of the DCM only. It does not
check that the DCM is configured properly, and does not check if the DCM phase adjustment range is exceeded.
The following is a Microprocessor Hardware Specification (MHS) file example of how a DCM can be connected to
MPMC to allow the MPMC Static PHY control registers to control DCM phase.
BEGIN mpmc
.
.
.
PORT MPMC_DCM_PSINCDEC = Static_Phy_DCM_PSINCDEC
PORT MPMC_DCM_PSEN = Static_Phy_DCM_PSEN
PORT MPMC_DCM_PSDONE = Static_Phy_DCM_PSDONE
END
BEGIN dcm_module
PARAMETER INSTANCE = dcm_2
PARAMETER HW_VER = 1.00.d
PARAMETER C_CLK0_BUF = TRUE
PARAMETER C_CLKIN_PERIOD = 10.000000
PARAMETER C_CLK_FEEDBACK = 1X
PARAMETER C_DLL_FREQUENCY_MODE = LOW
PARAMETER C_PHASE_SHIFT = 0
PARAMETER C_CLKOUT_PHASE_SHIFT = VARIABLE
PARAMETER C_EXT_RESET_HIGH = 0
PORT CLKIN = MPMC_Clk0
PORT CLK0 = MPMC_Clk_Mem
PORT CLKFB = MPMC_Clk_Mem
PORT RST = DCM_1_lock
PORT LOCKED = DCM_all_locked
PORT PSCLK = MPMC_Clk0
PORT PSINCDEC = Static_Phy_DCM_PSINCDEC
PORT PSEN = Static_Phy_DCM_PSEN
PORT PSDONE = Static_Phy_DCM_PSDONE
END
DS643 February 22, 2013
www.xilinx.com
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Product Specification