DS643 Datasheet, PDF (197/216 Pages) Xilinx, Inc – Soft Direct Memory Access (SDMA) support

LogiCORE IP Multi-Port Memory Controller (v6.06.a)
Table 95: NPI Latency and Throughput (Cont’d)
Number of
Ports
1
2
1
2
1
2
Pipeline
Settings
N/A
N/A
N/A
N/A
N/A
N/A
Memory Interface
DDR2/DDR3 @ 400 MHz
16 bits / NPI @ 100 MHz
DDR2/DDR3 @ 400 MHz
16 bits / NPI @ 100 MHz
DDR2/DDR3 @ 400 MHz
16 bits / NPI @ 100 MHz
DDR2/DDR3 @ 400 MHz
16 bits / NPI @ 100 MHz
DDR2/DDR3 @ 400 MHz
16 bits / NPI @ 100 MHz
DDR2/DDR3 @ 400 MHz
16 bits / NPI @ 100 MHz
NPI Width MPMC NPI
(Bits) Burst Type
64
16 Word Burst
64
16 Word Burst
64
32 Word Burst
64
32 Word Burst
64
64 Word Burst
64
64 Word Burst
Initial
Transaction
Latency
(MPMC_Clk0)
N/A⁽¹⁾
N/A⁽¹⁾
N/A⁽¹⁾
N/A⁽¹⁾
N/A⁽¹⁾
N/A⁽¹⁾
Maximum Total
Data Throughput
(MB/s)
655
642
800
910
801
1150
Notes:
1. Latency on writes is not characterized because the MPMC allows write data to pushed in before or after the address request.
Notes on NPI Throughput
1. NPI throughput increases with burst size so the 64 word bursts offer the highest maximum bandwidth, but
might increase the delay on other ports.
2. The throughput of the NPI interface is limited to a 64-bit wide datapath running at the memory clock speed.
Because the memory can have up to a 64-bit DDR interface (128-bit wide SDR datapath), it is possible that a
single NPI port might not be able to access the full available bandwidth of the memory. In such situations,
multiple NPI ports could be needed to fully utilize the memory in systems requiring highest throughput.
3. The MPMC control logic does not support row or bank management. After each NPI transaction, the row and
bank that was accessed is closed with a precharge.
PLB PIM Latency and Throughput
Table 96 provides latency and throughput of each PLB PIM port with performance information for various MPMC
and PLB PIM configurations.
Table 96: PLB PIM Latency and Throughput
Pipeline
Settings
Memory Interface NPI Width
PLB Burst
Type
Spartan-3 FPGA Generation Reads
Default
DDR@100 MHz 32 bits
Default
DDR2@133 MHz 16 bits
Default
DDR2@133 MHz 32 bits
Default
DDR@83 MHz 16 bits
All Pipelines Off DDR@83 MHz 16 bits
Spartan-3 FPGA Generation Writes
Default
DDR@100 MHz 32 bits
Default
DDR2@133 MHz 16 bits
Default
DDR2@133 MHz 32 bits
64
16 Doublewords
32
16 Words
64
16 Doublewords
32
16 Words
32
16 Words
64
16 Doublewords
32
16 Words
64
16 Doublewords
Memory to
PLB Clock
Ratio
Initial
Transaction
Latency (PLB
Clocks)
Maximum
Total Data
Throughput of
a PLB Port
(MB/s)
1:1
29
507
2:1
17
185
2:1
17
371
1:1
29
211
1:1
25
221
1:1
4
266
2:1
4
118
2:1
4
237
DS643 February 22, 2013
www.xilinx.com
197
Product Specification