DS643 Datasheet, PDF (34/216 Pages) Xilinx, Inc – Soft Direct Memory Access (SDMA) support

LogiCORE IP Multi-Port Memory Controller (v6.06.a)
Table 29: Debug Register Summary
Summary
Grouping
MPMC_CTRL Base Address
+ Offset (hex)
MIG PHY
C_MPMC_CTRL_BASEADDR + 0x2000
Register
Name
Access
Type
See Common
MIG PHY
Debug
Registers,
page 34
See Common
MIG PHY
Debug
Registers,
page 34
Default
Value (hex)
Based on
parameter
settings
Description
MIG PHY Debug Registers
Table 30 through Table 33 list the debug registers that are common to all devices and debug registers that are
device-specific. The address offset listed in these tables should be added to C_MPMC_CTRL_BASEADDR to calculate
the address location of these registers.
Common MIG PHY Debug Registers
Table 30: Common MIG PHY Debug Registers
Register Name
Base Address/
Offset from
C_MPMC_CTRL
BASEADDR (in hex)
Bits
0:31
Field Name
0:30
unused
CALIB_RST_CTRL 0x2000
31
REG_DEFAULT_ON_RST
The following registers are only valid if C_INCLUDE_ECC_SUPPORT = 1
ECC_DEBUG
0
ECC_BYTE_ACCESS_EN
0x2010
1:31
unused
0:7
ECC Read Data0
ECC_READ_DATA 0x2014
8:15
16:23
ECC Read Data1
ECC Read Data2
24:31 ECC Read Data3
ECC_WRITE_DATA 0x2018
0:7
8:15
16:23
24:31
ECC Write Data0
ECC Write Data1
ECC Write Data2
ECC Write Data3
Access
Type
R/W
R/W
R
R
R
R
R/W
R/W
R/W
R/W
Default
Value
Description
0 = MPMC reset does not change
control registers.
1
1 = Upon MPMC reset, set all
calibration control registers back to
default values (except this register).
0 = ECC byte data is controlled by the
normal ECC logic.
0
1 = Enable debug access to the ECC
byte lane to read/write the ECC byte
data directly.
Data read from ECC byte lane on the
0
first byte of the data in the four beat
memory burst.
Data read from ECC byte lane on the
0
second byte of the data in the four beat
memory burst.
Data read from ECC byte lane on the
0
third byte of the data in the four beat
memory burst.
Data read from ECC byte lane on the
0
fourth byte of the data in the four beat
memory burst.
0
First byte of ECC data in the four beat
memory burst to be written out.
0
Second byte of ECC data in the four
beat memory burst to be written out.
0
Third byte of ECC data in the four beat
memory burst to be written out.
0
Fourth byte of ECC data in the four
beat memory burst to be written out.
DS643 February 22, 2013
www.xilinx.com
34
Product Specification