DS643 Datasheet, PDF (38/216 Pages) Xilinx, Inc – Soft Direct Memory Access (SDMA) support

LogiCORE IP Multi-Port Memory Controller (v6.06.a)
Virtex-5 FPGA MIG PHY Debug Registers
Table 33: Virtex-5 FPGA MIG PHY Debug Registers
Register Name
Base Address/
Offset from
C_MPMC_CTRL
BASEADDR (in hex)
Bits
0:31
Field Name
0:5 unused
6 IDELAYCTRL_RDY_O
V5_CALIB_REG
0x2400
7 IDELAYCTRL_RDY_I
8:12 unused
13 FORCE_INITDONE
14 FORCE_INITDONE_VAL
15 MIG_INIT_DONE
V5_CALIB_REG
0x2400
16:30 unused
31 HW_CALIB_ON_RESET
0 unused
1:7
BIT_ERR_INDEX
8:11 unused
V5_CALIB_STATUS 0x2404 _{12:15 DONE_STATUS}
16:27 unused
28:31 ERR_STATUS
Access Default
Type Value
Description
Status of MPMC_Idelayctrl_Rdy_O.
R
0
0 = not ready
1 = ready
Status of MPMC_Idelayctrl_Rdy_I.
R
0
0 = not ready
1 = ready
0 = Allow hardware calibration engine to
R/W
0
drive MPMC INIT_DONE signal.
1 = Force MPMC INIT_DONE signal to be
equal to FORCE_INITDONEVAL.
R/W
0
Value to set MPMC INIT_DONE when
FORCE_INITDONE = 1.
0 = incomplete.
1 = MIG_HW_CALIBRATION initialization is
complete;
R
0
Note: HW calibration could be
complete but the INIT_DONE signal
from the PIM might be masked by the
FORCE_INITDONE signal.
Calibrate HW upon reset.
1 = Start memory hardware calibration
R/W
1
engine upon MPMC reset
0 = Do not run hardware calibration engine
upon MPMC reset
R
0
When a calibration error is reported, this
field indicates which bit DQ is failing.
4-bit calibration completion status:
R
0
0 =Incomplete
1 = Complete
4-bit calibration error status.
R
0
0 = no error
1 = error
DS643 February 22, 2013
www.xilinx.com
38
Product Specification