DS643 Datasheet, PDF (205/216 Pages) Xilinx, Inc – Soft Direct Memory Access (SDMA) support

LogiCORE IP Multi-Port Memory Controller (v6.06.a)
MPMC Core (LUT, FF, and Slice) Resource Utilization
Table 101 provides MPMC Core LUT and FF resource utilization. This includes the PHY, arbiter, control logic, and
datapath (using block RAM FIFOs) up to the internal NPI interfaces. PIM resource utilizations are provided
separately in the tables that follow. An estimate of Slice utilization is also provided for reference. The reported Slice
utilization numbers correspond to default slice packing effort for a medium full FPGA. The Slice utilization might
vary in actual systems due to factors such as the fullness of the device, Slice packing effort, and the amount of Slice
merging with other logic in the system.
Table 101: LUT and Flip Flop Utilization Estimates⁽¹⁾
FPGA
Family
Memory
Width
Memory Type
Base Single Port MPMC Core Size
Each Additional Port Size
LUT
FF
Slice
LUT
FF
Slice
Utilization Utilization Utilization Utilization Utilization Utilization
Spartan-3
Generation
16⁽²⁾ DDR/DDR2
340-390
850-970
620-720
180-200
220-250
210-240
Spartan-3
Generation
32
DDR/DDR2
450-510
1160-1330
840-970
170-200
250-290
220-260
Virtex-4
32
DDR/DDR2
1210-1390
1290-1480
1250-1440
250-290
310-360
280-320
Virtex-4
64
DDR/DDR2
2070-2380
2080-2390
2080-2390
240-280
350-410
290-340
Virtex-5
32
DDR/DDR2
960-1100
1410-1620
640-740
170-190
280-320
120-140
Virtex-5
64
DDR/DDR2
1770-2030
2050-2360
1030-1200
200-230
340-390
140-170
Virtex-6
32
DDR2/DDR3
2400-2600
3300-3600
1040-1200
150-250
320-450
140-180
Spartan-6
16
LPDDR/DDR/
DDR2/DDR3
520-560
320-360
200-250
80-100
120-190
40-70
Notes:
1. The size values provided assume that, on average, half the ports have 32-bit NPI interfaces.
2. If all ports have 32-bit NPI interfaces the datapath size would be further reduced because a 32-bit NPI has the same SDR data width as a 16-bit
DDR/DDR2 memory.
XCL PIM LUT and FF Resource Utilization
Table 102 provides the XCL PIM LUT, FF, and Slice resource utilization.
Table 102: XCL PIM LUT, FF, and Slice Resource Utilization
FPGA Family
SUBTYPE
LUT Utilization
Spartan-3
IXCL
150
Spartan-3
DXCL
168
Virtex-4
IXCL
161
Virtex-4
DXCL
194
Virtex-5/Virtex-6/Spartan-6
IXCL
189
Virtex-5/Virtex-6/Spartan-6
DXCL
207
FF Utilization
107
121
119
129
112
131
Slice Utilization
115
129
134
152
101
118
DS643 February 22, 2013
www.xilinx.com
205
Product Specification