DS643 Datasheet, PDF (67/216 Pages) Xilinx, Inc – Soft Direct Memory Access (SDMA) support

LogiCORE IP Multi-Port Memory Controller (v6.06.a)
ECC encode functionality adds latency to Writes. RMW support adds one cycle of latency to multiplex in Read data
(in addition to latency of the full Read transaction.) The Control state machines support the additional cycles of
latency between Write FIFO pop and data appearing at the PHY interface.
For debugging and testing, the ECC encode process allows you to insert single or double bit errors into the data
being written for test purposes. The error insertion logic can be parameterized out.
ECC Memory Organization and Word Size
Table 42 describes the ECC word size and number of extra memory data bits needed for different organizations of
memory. The RdModWr flag must be set according to the alignment across the ECC word size over a memory burst
length of 4.
Note: The PHY data calibration algorithm requires that a full ECC byte lane be present on the board although fewer bits might
be used by the ECC algorithm.
Table 42: ECC Word Size
Memory Type
Memory Data
Width
Physical Memory ECC Data Width
(C_NUM_ECC_BITS)
ECC Word Size
DDR/DDR2
8
DDR/DDR2
16
8
2 Instances of 8 + 5 Check Bits
8
2 Instances of 16 + 6 Check Bits
DDR/DDR2
32
DDR/DDR2
64
8
2 Instances of 32 + 7 Check Bits
8
2 Instances of 64 + 8 Check Bits
SDRAM
8
SDRAM
16
5
8 + 5 Check Bits
6
16 + 6 Check Bits
SDRAM
32
7
32 + 7 Check Bits
SDRAM
64
8
64 + 8 Check Bits
ECC Registers
Table 27, page 32 summarizes the ECC related registers which are included with the ECC logic for the MPMC when
ECC is enabled (C_INCLUDE_ECC_SUPPORT = 1). The following subsections describe each register in greater detail
and provide the bit definitions.
DS643 February 22, 2013
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