DS643 Datasheet, PDF (77/216 Pages) Xilinx, Inc – Soft Direct Memory Access (SDMA) support

LogiCORE IP Multi-Port Memory Controller (v6.06.a)
Performance Monitor Clear Register
The Performance Monitor Clear register (PMCLR) facilitates clearing the block RAMs used for the PM data bins
back to 0. It also used to clear the dead cycle counters and global cycle counter to 0.
This is a write-only register. Writing a 1 to the clear bits clears the counters immediately, and starts the clearing of
the data bins. Because the data bins are stored in a block RAM, it takes approximately 512 clock cycles to clear the
data bins to 0. To monitor the status of the clear, check the PMSTATUS register.
Table 53 describes the PMCLR register bits.
Table 53: PMCLR Register Bit Definitions
Bit(s)
0
1
2
3
4
5
6
7
8:14
15
16
17
18
19
20
21
22
23
Name
PM0_DATABIN_CLR
PM1_DATABIN_CLR
PM2_DATABIN_CLR
PM3_DATABIN_CLR
PM4_DATABIN_CLR
PM5_DATABIN_CLR
PM6_DATABIN_CLR
PM7_DATABIN_CLR
Reserved
PM_GCC_CLR
PM0_DCC_CLR
PM1_DCC_CLR
PM2_DCC_CLR
PM3_DCC_CLR
PM4_DCC_CLR
PM5_DCC_CLR
PM6_DCC_CLR
PM7_DCC_CLR
Core
Access
W
W
W
W
W
W
W
W
NA
W
W
W
W
W
W
W
W
W
Reset
Value
X
X
X
X
X
X
X
X
NA
X
X
X
X
X
X
X
X
X
Description
1 = Clear all data bin storage PM0
1 = Clear all data bin storage PM1
1 = Clear all data bin storage PM2
1 = Clear all data bin storage PM3
1 = Clear all data bin storage PM4
1 = Clear all data bin storage PM5
1 = Clear all data bin storage PM6
1 = Clear all data bin storage PM7
Reserved
1= Clear Dead Cycle Counter
1= Clear Dead Cycle Counter Port 0
1= Clear Dead Cycle Counter Port 1
1= Clear Dead Cycle Counter Port 2
1= Clear Dead Cycle Counter Port 3
1= Clear Dead Cycle Counter Port 4
1= Clear Dead Cycle Counter Port 5
1= Clear Dead Cycle Counter Port 6
1= Clear Dead Cycle Counter Port 7
DS643 February 22, 2013
www.xilinx.com
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Product Specification