DS643 Datasheet, PDF (182/216 Pages) Xilinx, Inc – Soft Direct Memory Access (SDMA) support

LogiCORE IP Multi-Port Memory Controller (v6.06.a)
8-Word, Cacheline Read with Back-to-Back Transfers
Figure 51 shows the following:
• A 64-bit NPI.
• There are two back-to-back, 8-word cacheline, Read transfers.
• First address is acknowledged same cycle as requested.
• Second address is acknowledged cycle after request.
• There is no gap between address requests.
• The addresses are on doubleword boundaries.
• The RdFIFO_RdWdAddr indicates that data is returned target-word first.
• There is a one cycle gap between read data for first request and second request. This could be more or less
cycles depending on arbitration and pipeline settings.
• There are three cases of possible RdFIFO_Latency values.
• A Spartan-6 FPGA implementation does not allow overlapping transactions. The AddrAck response on R1
does not occur until after the data from the first transaction completes.
X-Ref Target - Figure 51
MPMC_CLK0
AddrReq
AddrAck
Addr[31:0]
RNW
Size[3:0]
RdModWr
R0
R0
0x10
0x2
R1
R1
0x28
0x2
InitDone
RdFIFO_Empty
RdFIFO_Pop
RdFIFO_Flush
RdFIFO_Latency[1:0]
RdFIFO_Data[63:0]
RdFIFO_RdWdAddr[3:0]
0x0
D00
D10
D20
D30
0x4
0x6
0x0
0x2
D01
D11
D21
D31
0x2
0x4
0x6
0x0
Case 1
RdFIFO_Latency[1:0]
RdFIFO_Data[63:0]
RdFIFO_RdWdAddr[3:0]
RdFIFO_Latency[1:0]
RdFIFO_Data[63:0]
RdFIFO_RdWdAddr[3:0]
0x1
D00
D10
D20
D30
0x4 0x6 0x0 0x2
D01
D11
D21
D31
0x2 0x4 0x6 0x0
0x2
D00
D10
D20
D30
0x4
0x6
0x0
0x2
D01
D11
D21
D31
0x2
0x4
0x6
0x0
Figure 51: 64-Bit, NPI 8-Word Cacheline Read with Back-to-Back Transfers
Case 2
Case 3
X11006
DS643 February 22, 2013
www.xilinx.com
182
Product Specification