DS643 Datasheet, PDF (126/216 Pages) Xilinx, Inc – Soft Direct Memory Access (SDMA) support

LogiCORE IP Multi-Port Memory Controller (v6.06.a)
Soft Direct Memory Access Controller PIM for LocalLink Interfaces
The Soft Direct Memory Access (SDMA) Controller PIM, which is integrated into the MPMC, provides
high-performance Direct Memory Access (DMA) for streaming data. The SDMA provides two channels, one for
receiving data and one for transmitting data. Transmit and Receive are accomplished through two LocalLink
interfaces.
This section contains the following subsections:
• SDMA Features
• SDMA Overview
• SDMA Operation
• DMA Operation Descriptors
• SDMA Error Conditions
• Managing SDMA Descriptors
• SDMA LocalLink Interface
• SDMA Interrupts and Errors
• SDMA Transaction Timing
• SDMA Registers
SDMA Features
The SDMA Controller for LocalLink interfaces contains the following features:
• Direct plug-in to MPMC
• Simultaneous, independent Transmit and Receive DMA operations
• Per-channel Interrupt Event reporting
• Interrupt Coalescing
• Xilinx PLB v4.6 interface for control as a register access
• User-defined LocalLink headers and footers (for use with functions such as checksum off loading)
• Dynamic Scatter Gather Buffer Descriptor modification
• SDMA supports the following configurations only:
- 16-, 32-, and 64-bit for DDR
- 32- and 64-bit for SDRAM
- All widths in Spartan-6 and Virtex-6 FPGAs
SDMA Overview
The SDMA uses a Native Port Interface (NPI), two LocalLink interfaces, and a PLB interface. The NPI connects the
SDMA controller into the MPMC PIM. The two LocalLink interfaces, a Transfer (TX) and a Receive (RX), provide
full duplex LocalLink device access to the SDMA. The PLB interface allows the CPU to interact with the SDMA for
initiating DMA processes or status gathering. The PLB and LocalLink data and address signals are labelled with
big-endian bit/byte ordering as illustrated in Big-Endian Memory Data Types, page 86.
DS643 February 22, 2013
www.xilinx.com
126
Product Specification