DS643 Datasheet, PDF (120/216 Pages) Xilinx, Inc – Soft Direct Memory Access (SDMA) support

LogiCORE IP Multi-Port Memory Controller (v6.06.a)
Soft Calibration Module
The MPMC code contains the same Soft Calibration Module functionality described in the Spartan-6 FPGA Memory
Controller User Guide (a link to this document is available in Reference Documents, page 215). The soft calibration
module is used to tune internal termination resistors and to continuously tune the DQS tap delays to align the DQS
and DQ signals together. Both of these functions can be enabled or disabled using parameter settings.
It is generally required that DQS tuning be enabled. For input termination, there are three options: external discrete
termination resistors, internal tuned/calibration termination (not supported by LPDDR), and internal untuned
termination. When the Soft Calibration Module is enabled, the RZQ and/or ZIO I/O pins become active.
To enable DQS tuning, which is generally required for production silicon designs, the following MPMC parameters
must be set in the MHS file:
PARAMETER C_MEM_CALIBRATION_SOFT_IP = TRUE
PARAMETER C_MEM_SKIP_DYNAMIC_CAL = 0
Enabling DQS tuning makes the RZQ pin active and it must be properly connected on the board. When the internal
tuned input termination feature (also known as calibrated termination) is used, the following MPMC parameters
must be set in the MHS file:
PARAMETER C_MEM_CALIBRATION_SOFT_IP = TRUE
PARAMETER C_MEM_SKIP_IN_TERM_CAL = 0
Enabling tuned input termination makes the ZIO pin active and it must be properly used on the board. If the ZIO
pin is not used, do not connect it to the top-level port of the XPS design so that an unnecessary ZIO I/O pin location
constraint is not applied.
Note: Tuned input termination should not be used with LPDDR; therefore, LPDDR designs should not have ZIO connected to
the top level ports of the XPS design.
The use of internal untuned termination can be accomplished by setting IN_TERM=UNTUNED_SPLIT_<impedance> in
the system-level system.ucf for the DQ and DQS pins. For example:
NET MPMC_0_mcbx_dram_dq[*]IN_TERM=UNTUNED_SPLIT_50;
NET MPMC_0_mcbx_dram_dqsIN_TERM=UNTUNED_SPLIT_50;
NET MPMC_0_mcbx_dram_dqs_nIN_TERM=UNTUNED_SPLIT_50;
NET MPMC_0_mcbx_dram_udqsIN_TERM=UNTUNED_SPLIT_50;
NET MPMC_0_mcbx_dram_udqs_nIN_TERM=UNTUNED_SPLIT_50;
Consult the Spartan-6 FPGA Memory Controller User Guide for more information about input termination on the
MCB pins (a link to this document is available in Reference Documents, page 215).
MCB Bring-Up
For initial MCB bring-up on a new board, it is recommended to use the MIG tool initially to generate a standalone
synthesizable test bench for the MCB. The standalone MIG generated designs contains a traffic generator to send
transactions to the MCB as well as providing some facilities for debugging the physical interface. The standalone
MIG design can be used to validate the physical memory interface before using the MPMC. See UG388, Spartan-6
FPGA Memory Controller User Guide for additional information. Reference Documents, page 215 contains a link to
the document.
Unsupported MCB Features
The MPMC does not support the Self Refresh or Suspend modes of the MCB.
DS643 February 22, 2013
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Product Specification