DS643 Datasheet, PDF (63/216 Pages) Xilinx, Inc – Soft Direct Memory Access (SDMA) support

LogiCORE IP Multi-Port Memory Controller (v6.06.a)
Spartan-3, Virtex-4, and Virtex-5 FPGA Reset Logic
The basic MPMC core and each of the MPMC PIMs have a reset input. Internally these resets are ORed together to
create the master reset for the entire MPMC (including PIMs).
Note: It is not possible to reset an individual PIM or PORT of the MPMC without resetting everything.
The master reset is internally registered and synchronized before being distributed throughout MPMC; therefore,
the MPMC reset is a fully synchronous reset.
Reset should be held for a minimum of eight cycles of the slowest PIM clock. After reset, there should not be access
to any of the ports or control interfaces for 20 cycles of the MPMC_Clk. Table 41 provides a summary of reset logic.
Table 41: Reset Summary
Reset Name
Description
MPMC_Rst
Main MPMC reset.
<PIM>_Rst
See specific PIM documentation (which is located in Personality Interface Modules,
page 121) for more details.
Error Correction Code
The Error Correction Code (ECC) is enabled optionally using the C_INCLUDE_ECC_SUPPORT parameter control and
is supported on Spartan-3, Virtex-4, and Virtex-5 FPGAs.
The following subsections describe the ECC:
• ECC Features
• ECC Implementation
• ECC Read Data Handling
• ECC Need for Read Modify Write
• ECC Memory Organization and Word Size
• ECC Registers
• ECC Testing
ECC Features
The ECC features are:
• Supports 8-, 16-, 32-, and 64-bit wide SDRAM, DDR, and DDR2 memories.
• Provides Single Error Correction (SEC) and Double Error Detect (DED).
• Can generate interrupts when the number and type of errors reach a programmed threshold value.
• Supported on Spartan-3 FPGA MIG PHY for 8-, 16-, and 32-bit wide data.
• Supported with Static PHY.
ECC Implementation
ECC functionality is implemented by inserting the ECC decode and encode logic between the Physical Interface
(PHY) and datapath of the MPMC. Figure 5 shows the current MPMC PHY datapath connection for DDR/DDR2
memory.
DS643 February 22, 2013
www.xilinx.com
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Product Specification