DS643 Datasheet, PDF (214/216 Pages) Xilinx, Inc – Soft Direct Memory Access (SDMA) support

LogiCORE IP Multi-Port Memory Controller (v6.06.a)
In the ECC/PM/PHY/DBG tab, you can set:
• Enable Static PHY: Settings for:
- Power-on/reset Value of RDDATA_CLK_SEL Register
- Power-on/reset Value of RDDATA_SWAP_RISE Register
- Power-on/reset Value of RDENDELAY_CLK Register
• Enable Performance Monitor settings for:
- Dead Cycle Counter Width
- Shift Value of Trans Counter
- Enable Global Cycle Counter checkbox
- Global Cycle Counter Width
• Port Specific Performance Monitor checkboxes for:
- Enable Perf Mon.
- Enable Dead Cycle Counter
• Misc Settings
• Restore ECC/Debug Defaults
• Enable ECC
- ECC Default is On checkbox
- Include ECC Test checkbox
- SEC Threshold setting
- DEC Threshold setting
- PEC Threshold setting
Misc
When applicable, the Misc tab lets you set the following parameters:
• IODELAY Grouping
• IDELAYCTRL Constraint Locations (Hyphen separated)
• Number of IDELAYCTRL Elements
• Specifies Which Port’s Write FIFO is used for Memory Initialization
• Number of Requests MPMC can Queue per Port
• Perform Shorter Simulation Initialization
• MPMC PIMs Software High Address
• MMC_ADV Constraint Location (internal)
• MMCM_ADV Constraint Location (external)
When the option is grayed out, the parameter does not apply.
DS643 February 22, 2013
www.xilinx.com
214
Product Specification