DS643 Datasheet, PDF (129/216 Pages) Xilinx, Inc – Soft Direct Memory Access (SDMA) support

LogiCORE IP Multi-Port Memory Controller (v6.06.a)
Figure 16 and Figure 17 show descriptors organized into a linked list. The SDMA successively performs the DMA
operations specified in the descriptors up to and including the descriptor with the CURDESC_PTR = TAILDESC_PTR.
X-Ref Target - Figure 16
CURDESC_PTR
Register Value
NXTDESC_PTR
CURBUF_ADDR
CURBUF_LENGTH
STS_CTRL_APP0
APP1
APP2
APP3
APP4
NXTDESC_PTR
CURBUF_ADDR
CURBUF_LENGTH
STS_CTRL_APP0
APP1
APP2
APP3
APP4
NXTDESC_PTR
CURBUF_ADDR
CURBUF_LENGTH
STS_CTRL_APP0
APP1
APP2
APP3
APP4
NXTDESC_PTR
CURBUF_ADDR
CURBUF_LENGTH
STS_CTRL_APP0
APP1
APP2
APP3
APP4
NXTDESC_PTR
CURBUF_ADDR
CURBUF_LENGTH
STS_CTRL_APP0
APP1
APP2
APP3
APP4
NXTDESC_PTR
CURBUF_ADDR
CURBUF_LENGTH
STS_CTRL_APP0
APP1
APP2
APP3
APP4
NXTDESC_PTR
CURBUF_ADDR
CURBUF_LENGTH
STS_CTRL_APP0
APP1
APP2
NXTDESC_PTR
CURBUF_ADDR
CURBUF_LENGTH
STS_CTRL_APP0
APP1
APP2
Figure 16: Linked List of Descriptors
Address of this
Descriptor = TAILDESC
Figure 17 shows descriptors organized into a buffer ring for dynamic descriptor update. The buffer ring is for a
Transmit channel as evidenced by STS_CTRL_APP0.SOP=1 and STS_CTRL_APP0.EOP=1 tags.
Packet 4 is specified by a single descriptor and others by more than one consecutive descriptor. The address of the
last ready packet is equal to the TAILDESC_PTR, giving a sentinel position in the ring.
Note: Even when descriptors are contiguously allocated, they are required to be linked through the NXTDESC_PTR field.
DS643 February 22, 2013
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Product Specification