DS643 Datasheet, PDF (13/216 Pages) Xilinx, Inc – Soft Direct Memory Access (SDMA) support

LogiCORE IP Multi-Port Memory Controller (v6.06.a)
Table 4: Per-Port Parameters (Cont’d)
I/O Signal Name
C_PI<Port_Num>_PM_DC_CNTR^(2),(10)
Default
Value
1
Allowable
Values
0,1
Description
Enable Dead Cycle Counter.
Notes:
1. Only valid if C_PIM_BASETYPE is not 4 (NPI) and C_ALL_PIMS_USE_SHARED_ADDRESSES is 0.
2. Only valid if C_PM_ENABLE = 1.
3. If C_PM<Port_Num>_PM_USED is set to 1, then C_PI<Port_Num>_ADDRACK_PIPELINE must be set to 1 to monitor correctly.
4. C_PI<Port_Num>_RD_FIFO_MEM_PIPELINE settings must all be the same from port 0 to port <C_NUM_PORTS-1>.
For example, on a four-port design, ports 0 to 3 must have the same C_PI<Port_Num>_RD_FIFO_MEM_PIPELINE settings.
5. C_PI<Port_Num>_WR_FIFO_MEM_PIPELINE settings must all be the same from port 0 to port <C_NUM_PORTS-1>.
For example, on a four-port design, ports 0 to 3 must have the same C_PI<Port_Num>_WR_FIFO_MEM_PIPELINE settings.
6. Write FIFOs are automatically disabled in an MPMC port that is an IXCL or IPLB subtype. There is no need to manually disable write FIFOs
in an IXCL or IPLB configured port.
7. C_PIM<Port_Num>_BASEADDR+C_PIM<Port_Num>_OFFSET represents the base physical memory address that the corresponding
port is allowed to access.
For example, if C_PIM<Port_Num>_OFFSET is 0x00000000, C_PIM<Port_Num>_BASEADDR represents the physical address of
memory. If your total memory size is 0x03FFFFFF, a C_PIM_<Port_Num>_BASEADDR value of 0x00000000 goes to physical address
0x00000000.
A value of 0x01000000 goes to physical address 0x01000000. A value of 0x04000000 goes to physical address 0x00000000.
If you increase the C_PIM_<Port_Num>_OFFSET to 0x02000000, a C_PIM_<Port_Num>_BASEADDR value of 0x00000000 goes to
physical address 0x02000000. A value of 0x01000000 goes to physical address 0x03000000. A value of 0x04000000 goes to physical
address 0x02000000.
8. C_PIM<Port_Num>_HIGHADDR+C_PIM<Port_Num>_OFFSET represents the high physical memory address that the corresponding port
is allowed to access.
9. Used only for XCL<Port_Num>_B port when C_XCL<Port_Num>_B_IN_USE is set to 1.
10. Not supported on Spartan-6 FPGAs.
11. When using the VFBC PIM on Spartan-6 FPGAs, the allowable values of this parameter are BRAM and DISABLED. If set to DISABLED,
then VFBC unidirectional optimizations are performed. BRAM in this case is synonymous with ENABLED.
Personality Interface Module (PIM) Parameters
XCL PIM Design Parameters
Table 5 lists the XCL PIM design parameters.
Table 5: XCL Design Parameters
Parameter Name
C_XCL<Port_Num>_LINESIZE⁽¹⁾
Default
Value
4
Allowable
Values
1,4,8,16
C_XCL<Port_Num>_WRITEXFER⁽¹⁾
1
0, 1, 2
C_XCL<Port_Num>_B_LINESIZE^(1),(2)
4
1,4,8,16
C_XCL<Port_Num>_PIPE_STAGES
2
0,1, 2, 3
C_XCL<Port_Num>_B_WRITEXFER^(1),(2)
1
0, 1, 2
C_XCL<Port_Num>_B_IN_USE
0
0, 1
Notes:
1. Valid when C_PIM<Port_Num>_BASETYPE = 1 (XCL) only
2. Valid when C_XCL<Port_Num>_B_IN_USE = 1 only
Description
Number of words per transaction.
XCL write transfer type:
0 = No write transfers.
1 = Single write transfers only.
2 = Cache line transfer only.
Number of words per transaction.
Include additional pipeline stages:
0 = None
1 = Read FIFO
2 = Read FIFO and Empty
3 = Read FIFO and Empty and Access FIFOs
XCL write transfer type:
0 = No write transfers.
1 = Single write transfers only.
2 = Cache line transfer only.
XCL B Port Enable. This parameter enables another XCL BUS on
the same MPMC Port.
1 = Enable XCL B Port.
0 = Disable XCL B Port.
DS643 February 22, 2013
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Product Specification