DS643 Datasheet, PDF (127/216 Pages) Xilinx, Inc – Soft Direct Memory Access (SDMA) support

LogiCORE IP Multi-Port Memory Controller (v6.06.a)
Figure 15 provides a high-level block diagram of SDMA.
X-Ref Target - Figure 15
PLB
plbv46_slave_single
SDMA
NPI Signals
NPI
DMA Engine and
Control Logic
RX LocalLink
Interface
RX LocalLin
TX LocalLink
Interface
TX LocalLin
Figure 15: High Level SDMA Block Diagram
SDMA Operation
Scatter Gather Operation
Scatter Gather operation has the concept of descriptor chaining which allows a packet to be described by more than
one descriptor. Typical use for this feature is to allow storing or fetching of ethernet headers from one location in
memory and payload data from another location. Software applications that can take advantage of this can improve
throughput.
SDMA uses Start of Packet bit (SOP) and End of Packet bit (EOP) to delineate packets in a buffer descriptor chain.
When the DMA fetches a descriptor with the STS_CTRL_APP0.SOP bit set this triggers the start of a packet. The
packet continues fetching subsequent descriptors until a descriptor with the STS_CTRL_APP0.EOP bit is set.
For the receive channel, when a packet has been completely received the SDMA acquires the footer fields of the
LocalLink stream and writes these values to APP0 through APP4 fields of the last descriptor. SDMA also sets
STS_CTRL_APP0.EOP=1 indicating to the software that the current receive buffer as described by the descriptor
contains the last of the packet data.
For the transmit channel, SDMA uses the STS_CTRL_APP0.EOP bit. When SDMA determines that the
STS_CTRL_APP0.EOP bit is set in STS_CTRL_APP0, the SDMA completes the currently requested transfer and then
terminates the LocalLink transfer with a LocalLink End of Frame (EOF).
Starting and Stopping DMA Operations
DMA operations can be started by writing an address to the respective TAILDESC_PTR register. When the start
condition is met, CHNL_STS.EngBusy of the respective channel is set and the SDMA fetches the first descriptor that
is pointed to by the address in the CURDESC_PTR register.
DMA descriptor processing continues until a descriptor that has the TAILDESC_PTR = CURDESC_PTR for the
respective channel has finished being processed.
DS643 February 22, 2013
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Product Specification