DS643 Datasheet, PDF (115/216 Pages) Xilinx, Inc – Soft Direct Memory Access (SDMA) support

LogiCORE IP Multi-Port Memory Controller (v6.06.a)
Arbitration Algorithms
The MCB inside the MPMC can be programmed to support various arbitration algorithms. See Multi-Port
Arbitration Algorithms, page 52 for more information.
Datapath and Physical Memory Interface
The MCB implements control path FIFOs, read data FIFOs, and write data FIFOs to buffer transactions at the ports
while the memory controller core arbitrates transactions and executes them over fast paths to memory.
The MCB supports DDR, LPDDR, DDR2, and DDR3 physical memories of 4, 8, or 16 bits. These memories are
generally limited to a single component and a fixed set of support memory device manufacturers and parts.
Consult the Spartan-6 FPGA Packaging and Pinout Specification and the Spartan-6 FPGA Memory Controller User Guide
for important information about the supported memory devices, board design, limitations, operating ranges, and
other design considerations. Those documents might list additional limitations not described here.
Memory Interface Generator (MIG)
For designs with custom or standalone use of the MCB, Xilinx provides a Memory Interface Generator (MIG) tool,
available in the CORE Generator tool that helps a user to configure the MCB and use it in a custom design.
When using MPMC with a Spartan-6 FPGA, it is not necessary to use the MIG tool separately to configure the MCB.
The configuration of the MCB is handled completely within the XPS tool framework and the MPMC core. Using
MPMC parameters and the MPMC IP Configuration GUI, the necessary information for configuring the MCB is
generated. See MCB PIM, page 187 for more information.
However, it can be useful to become familiar with the MIG tool as a guide for exploring the features, board design
considerations, and capabilities of the MCB. It is not necessary to set the IOSTANDARD or pin LOC constraints in the
system UCF for the FPGA pins connected to the memory device. This information is obtained automatically from
the value of C_MCB_LOC and the underlying MIG tool when Platgen is run to set the values in a core level UCF
located at: <EDK Project Directory>/implementation/<core_instance_name>_wrapper.ncf.
Any of these core level constraints can be overridden by the system level system.ucf, but this is Not
recommended. When RZQ and ZIO pins are used (C_MEM_CALIBRATION_SOFT_IP = TRUE), the selected pinout for
the RZQ and ZIO pins must be specified with the C_MCB_RZQ_LOC and the C_MCB_ZIO_LOC parameters,
respectively. There are more than one usable I/O location for the RZQ and ZIO pins. The list of available pins can be
selected in the MPMC IP Configurator and vary based on the chosen bank for the memory controller. Choose the
pin that matches the board layout of the FPGA. If a pin layout has not yet been chosen, the recommended value is
identified in the GUI. Verify all MCB pinouts with the Spartan-6 FPGA Packaging and Pinout Specification and the
Spartan-6 FPGA Memory Controller User Guide before beginning a board design. A link to these documents is
provided in Reference Documents, page 215.
DS643 February 22, 2013
www.xilinx.com
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Product Specification