DS643 Datasheet, PDF (39/216 Pages) Xilinx, Inc – Soft Direct Memory Access (SDMA) support

LogiCORE IP Multi-Port Memory Controller (v6.06.a)
Table 33: Virtex-5 FPGA MIG PHY Debug Registers (Cont’d)
Register Name
Base Address/
Offset from
C_MPMC_CTRL
BASEADDR (in hex)
Bits
0:31
Field Name
Access
Type
0:10 unused
11:15 RDEN_DLY<n>
R/W
16:18 unused
V5_CALIB_DQS_
GROUP0
0x2440
.
.
.
.
19:23 GATE_DLY<n>
R/W
.
.
V5_CALIB_DQS_ ^0x2460
GROUP8
24:30 unused
31 RD_SEL<n>
R/W
V5_CALIB_DQS_
TAP_CNT0
.
.
.
V5_CALIB_DQS_
TAP_CNT8
0:6 unused
7 DQS_TAP_CNT_INC<n>
0x2480
.
.
.
0x24A0
8:14 unused
15 DQS_TAP_CNT_DEC<n>
16:25 unused
26:31 DQS_TAP_CNT<n>
Wr Only
Wr Only
R
0:6 unused
V5_CALIB_GATE_
TAP_CNT0
.
.
,
V5_CALIB_GATE_
TAP_CNT8
V5_CALIB_DQ_
TAPCNT0
.
.
.
.V5_CALIB_DQ_
TAP_CNT71
0x24c0
.
.
.
0x24e0
0x2600
.
.
.
0x271c
7 GATE_TAP_CNT_INC<n>
8:14 unused
15 GATE_TAP_CNT_DEC<n>
16:25 unused
26:31 GATE_TAP_CNT<n>
0:6 unused
7 DQ_TAP_CNT_INC<n>
15 DQ_TAP_CNT_DEC<n>
16:25 unused
26:31 DQ_TAP_CNT<n>
Wr Only
Wr Only
R
Wr Only
Wr Only
R
Default
Value
Description
0
Number of cycles after read command until
read data is valid for DQS group<n>.
Number of cycles after read command until
0
clock enable for DQ byte group is
deasserted to prevent postamble glitch for
DQS group <n>.
Final read capture MUX set for positive or
0
negative edge capture for DQS group<n>:
0 = Pass
1 = Fail
N/A
DQS<n> IDELAY tap count increment, 1
tap increment per write.
N/A
DQS<n> IDELAY tap count decrement, 1
tap decrement per write.
DQS<n> IDELAY tap count.
0
0 = Pass
1 = Fail
N/A
GATE<n> IDELAY tap count increment, 1
tap increment per write.
N/A
GATE<n> IDELAY tap count decrement, 1
tap decrement per write.
0
GATE<n> IDELAY tap count.
N/A
DQ[<n> IDELAY tap count increment, 1 tap
increment per write.
N/A
DQ<n> IDELAY tap count decrement, 1
tap decrement per write.
0
DQ<n> IDELAY tap count.
DS643 February 22, 2013
www.xilinx.com
39
Product Specification