DS643 Datasheet, PDF (125/216 Pages) Xilinx, Inc – Soft Direct Memory Access (SDMA) support

LogiCORE IP Multi-Port Memory Controller (v6.06.a)
XCL Line Size and Write Transfers
The C_XCL<Port_Num>_LINESIZE parameter specifies whether the XCL line size is 1, 4, 8, or 16 words. This line
size is set for all XCL reads. The 4-, 8-, or 16-word transfers are target word first cacheline transfers. For Writes, the
C_XCL<Port_Num>_WRITEXFER parameter specifies whether XCL Write transactions are:
• 0 - Disabled
• 1 - One word only
• 2 - The same size as the Reads specified in C_XCL<Port_Num>_LINESIZE
If the XCL PIM is used, the NPI data width is fixed automatically at 32 bits. XCL data and address are labeled with
big-endian bit and byte ordering as described in Figure 8, page 86.
XCL Pipeline Stages
The C_XCL<Port_Num>_PIPE_STAGES parameter can be used to adjust the number of pipeline stages in the XCL
PIM. There are three different pipelines with four possible settings for C_XCL<Port_Num>_PIPE_STAGES:
• 0 - No pipelines are enabled.
• 1 - One pipeline is enabled: This setting enables a pipeline register on the output of the XCL Read data FIFO.
This pipeline helps cross clock boundaries on the read channel. Adds one cycle of Read latency.
• 2 - Two pipelines are enabled: This setting enables an additional pipeline on the NPI Read FIFO Empty signal.
This helps alleviate timing path on the NPI read FIFO control signals, and adds one cycle of Read latency.
• 3 - Three pipelines are enabled: This setting enables an additional pipeline on the output of the XCL Access
FIFO.
Note: Pipelines added in with values 1 and 2 each add a cycle of latency to each XCL Read. The pipeline added with value 3
might add one cycle of latency to both XCL Reads and XCL Writes.
XCL Clock Requirements
The XCL PIM runs at an integer ratio of the MPMC memory clock rate. This clock ratio is automatically detected
during reset and can be a ratio of either 1:1 or 2:1. The XCL PIM clock must be synchronous and rising edge-aligned
to the MPMC memory clock.
XCL Additional Information
For additional details on XCL, including signaling protocol and waveforms, see the MicroBlaze Processor Reference
Guide. Reference Documents, page 215 contains a link to the document.
DS643 February 22, 2013
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Product Specification