DS643 Datasheet, PDF (154/216 Pages) Xilinx, Inc – Soft Direct Memory Access (SDMA) support

LogiCORE IP Multi-Port Memory Controller (v6.06.a)
Processor Local Bus Version 4.6 PIM
The Processor Local Bus version 4.6 (PLB v4.6) PIM provides the interconnect from the PLB v4.6 bus to the MPMC.
This section has the following topics:
• PLB v4.6 PIM Features
• PLB v4.6 PIM Overview
• Supported NPI Transfer Types
• Supported PLB Master and Bus Widths
• Configuring PLB v4.6 for Point-To-Point or Shared Bus
• Configuring PLB v4.6 PIM SUBTYPES
• Supported Transactions by SUBTYPE
PLB v4.6 PIM Features
The PLB v4.6 PIM supports the following features:
• IBM CoreConnect 32-, 64-, and 128-bit PLB compatibility conforming to PLB v4.6 with Xilinx simplifications.
See Reference Documents, page 215 for links to more information.
• Access by 32-, 64-, and 128-bit masters. The PLB data and address signals are labelled with big-endian bit and
byte ordering as illustrated inBig-Endian Memory Data Types, page 86.
• Single, data-beat read and write data transfers
• Fixed-burst read and write data transfers
• 4- and 8-word, cacheline read and write transfers
• PLB Point-to-Point (P2P) configuration
• Supports 1:1 and 2:1 (MPMC:PIM) synchronous clock ratios (automatically detected during reset)
• PIM<Port_Num>_PLB_SAValid on PLB read transfers to minimize bubbles between reads
• 32-bit address offset (the optional address offset is added to the PLB transaction address to compute the
physical memory address to be accessed)
PLB v4.6 PIM Overview
PLB v4.6 PIM provides the interconnect from the PLB v4.6 bus to the MPMC.
Over NPI, PLB v4.6 PIM translates a PLB transaction into one or more NPI transactions. These NPI transactions can
be byte, half-word, word, 4- and 8-word, cacheline transactions. The NPI transactions type can be 16 word bursts or
32 word bursts also, depending on the value of C_SPLB<Port_Num>_NATIVE_DWIDTH.
If the generic C_SPLB<Port_Num>_NATIVE_DWIDTH is set to 64, the PIM requests 32 word NPI bursts from the
MPMC; however, if C_SPLB<Port_Num>_NATIVE_DWIDTH is set to 32, the PIM requests 16 word NPI bursts from
the MPMC. The PLB v4.6 PIM translates PLB transactions into these discrete NPI transactions. Because PLB bursts
can have a fixed length ranging from 1 to 16 data beats and can start at different addresses, the PIM must arrange
PLB data to fit the available set of NPI transaction types.
The PLB v4.6 PIM is configured by EDK to various subtypes based on the port to which the PIM is connected. The
SUBTYPEs are DPLB, IPLB, Single, and PLB:
• The DPLB SUBTYPE is chosen when the PIM is connected to a PowerPC 405 processor DPLB1 port using a
point-to-point connection.
DS643 February 22, 2013
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Product Specification