DS643 Datasheet, PDF (32/216 Pages) Xilinx, Inc – Soft Direct Memory Access (SDMA) support

LogiCORE IP Multi-Port Memory Controller (v6.06.a)
Table 25: PLB v4.6 PIM Dependencies (Cont’d)
Parameter
Affects
<Bus_Name>_AWIDTH
<Bus_Name>_PLB_ABus
<Bus_Name>_PLB_wrDBus
C_<Bus_Name>_DWIDTH
<Bus_Name>_Sl_rdDBus
<Bus_Name>_PLB_BE
C_<Bus_Name>_MID_WIDTH
<Bus_Name>_PLB_masterID
NPI Parameter and I/O Signal Dependencies
Table 26 lists the NPI parameter and I/O signal dependencies.
Table 26: NPI Parameter and I/O Signal Dependencies
Parameter Name
Affects Signals
C_PIM<Port_Num>_DATA_WIDTH
PIM<Port_Num>_WrFIFO_Data
PIM<Port_Num>_WrFIFO_BE
PIM<Port_Num>_RdFIFO_Data
Relationship Description
Width of the PLB Address Bus.
Width of the PLB Write Data Bus.
Width of the PLB Read Data Bus.
<Bus_Name>_PLB_BE =
C_<Bus_Name>_DWIDTH/8.
Width of the PLB Master ID Bus.
Relationship Description
Width of the data at each port and
corresponding byte enable.
Control and Status Registers
The MPMC pcore might contain various status and control registers depending on the configuration options. These
are all controlled through a single PLB v4.6 interface designated MPMC_CTRL. Additionally, each SDMA PIM also
contains its own control and status register PLB v4.6 interface to control the operation of DMA. The MPMC_CTRL
interface is composed of the following sections:
• ECC Register Summary
• Static PHY Register Summary
• MIG PHY Debug Register Summary
• Status Register Summary
• Performance Monitor Register Summary
• SDMA Register Summary
ECC Register Summary
The registers described in Table 27 are available only when ECC is enabled. See ECC Registers, page 67 for detailed
ECC register information.
Table 27: ECC Register Descriptions
MPMC_CTRL Base Address +
Offset (hex)
Register
Name
Access
Default
Type Value (hex)
Description
ECC Core
C_MPMC_CTRL_BASEADDR + 0x0
C_MPMC_CTRL_BASEADDR + 0x4
C_MPMC_CTRL_BASEADDR + 0x8
C_MPMC_CTRL_BASEADDR + 0xC
ECCC⁽¹⁾
ECCS⁽¹⁾
ECCSEC⁽¹⁾
ECCDEC⁽¹⁾
R/W⁽⁶⁾
R/ROW⁽²⁾
R/ROW⁽²⁾
R/ROW⁽²⁾
00000000⁽³⁾
00000000
00000000
00000000
ECC Control register.
ECC Status register.
ECC Single Bit Error Count register.
ECC Double Bit Error Count register.
C_MPMC_CTRL_BASEADDR + 0x10
C_MPMC_CTRL_BASEADDR + 0x14
ECCPEC⁽¹⁾
ECCADDR⁽¹⁾
R/ROW⁽²⁾
RO⁽⁵⁾
00000000
N/A
ECC Parity Field Single Bit Error Count
register.
ECC Error Address register.
DS643 February 22, 2013
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Product Specification