DS643 Datasheet, PDF (111/216 Pages) Xilinx, Inc – Soft Direct Memory Access (SDMA) support

LogiCORE IP Multi-Port Memory Controller (v6.06.a)
In Figure 12:
• The Tac is typically between 5 and 6 ns.
• The data capturing logic works on the positive edge of MPMC_Clk_Mem, which can be phase-adjusted using the
Static PHY interface or connected to a fixed clock source with the correct relative phase.
• This capture clock can be adjusted to maximize the size of the timing window for capturing data.
• The captured data is then re-synchronized to positive or negative edge of MPMC_Clk0 (set by
C_STATIC_PHY_RDDATA_CLK_SEL) before finally being pushed into the Read datapath FIFOs on MPMC_Clk0.
• The data capture clock cycle latency relative to the control signals can be set using parameter
C_STATIC_PHY_RDEN_DELAY and is affected by CAS latency, the use of registers on the board, and physical
delays relative to the clock period.
• The SDRAM PHY performs the power up initialization sequence and configuration of SDRAM with
user-specified values from the MHS file.
• When the MPMC is configured for SDRAM, the Static PHY is instantiated automatically. It is not necessary to
set C_USE_STATIC_PHY = 1 also.
Low Frequency SDRAM Clock and DCM Phase Adjustment Limits
In lower frequency SDRAM designs, generally under 100 MHz, the fine phase adjustment range of the DCM might
limit the available search range of the capture clock. This can limit the amount of margin in the Read data capture
window depending upon board delays and part delays.
If the Read data capture window is too small because the DCM fine adjustment range is limited, consider using
DCM outputs of CLK90, CLK180, or CLK270 to best center the DCM phase search window around the Read data.
This might require board delay or oscilloscope-based analysis.
For very low frequency SDRAM designs such as below 50 MHz, a fixed DCM output of CLK0, CLk90, CLK180, or
CLK270 usually can be connected directly to MPMC_Clk_Mem because this results in a sufficient Read data capture
window. In this case you might need to use experimentation or oscilloscope-based analysis to find the best fixed
clock phase (0, 90, 180, or 270). A modified static PHY calibration program or experimentation can then be used to
find the optimal settings for C_STATIC_PHY_RDDATA_CLK_SEL and C_STATIC_PHY_RDEN_DELAY for the given
MPMC_Clk_Mem clock. The CLK90 setting is a recommended starting point for very low frequency designs.
DS643 February 22, 2013
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Product Specification