DS643 Datasheet, PDF (28/216 Pages) Xilinx, Inc – Soft Direct Memory Access (SDMA) support

LogiCORE IP Multi-Port Memory Controller (v6.06.a)
Table 22: VFBC PIM I/O Signals (Cont’d)
Port Name
VFBC<Port_Num>_Wd_Full
VFBC<Port_Num>_Wd_Almost_Full
VFBC Read Data Interface
VFBC<Port_Num>_Rd_Clk
VFBC<Port_Num>_Rd_Reset^(1),(2)
VFBC<Port_Num>_Rd_Flush^(1),(3)
VFBC<Port_Num>_Rd_Read
VFBC<Port_Num>_Rd_End_Burst
VFBC<Port_Num>_Rd_Data
[C_VFBC<Port_Num>_RDWD_DATA_WIDTH-1:0]
VFBC<Port_Num>_Rd_Empty
VFBC<Port_Num>_Rd_Almost_Empty
Direction
Output
Output
Init
Status
Description
Write Data FIFO Full. High only when the write data FIFO
1
is full. The depth of the FIFO is set by the
C_VFBC<Port_Num>_RDWD_FIFO_DEPTH parameter.
Write Data FIFO Almost Full. High only when the write
1
data FIFO is almost full. Controlled by the
C_VFBC<Port_Num>_RD_AEMPTY_WD_AFULL_COUNT
parameter.
Input
Input
Input
Input
Input
Output
Output
Output
x
Read Data FIFO Clock:
Can be asynchronous from the MPMC_Clk0 Clock.
Read Data FIFO Reset (active-High).
When asserted, this command:
• Flushes the Read Data FIFO.
• Clears the current Read command from the command
x
FIFO.
Resetting the Read Data FIFO returns the internal
read/write FIFO pointers to zero. The current write
command is also removed from the command FIFO even
if the command has not completed.
Read Data FIFO Flush (active-High).
x
Asserting this command returns the internal read/write
FIFO pointers to zero. Unlike a FIFO reset, the current
read command is kept active in the command FIFO.
x
Read Data FIFO Pop (active-High).
Burst End.
Used only when the transfer is not a multiple of the burst
x
size. If the transfer ends on a non 32-word boundary, this
signal must be asserted High during the last word
transferred.
This signal is usually tied Low.
x
Read Data FIFO Data. The data is valid one clock cycle
after when the VFBC<Port_Num>_Rd_Read is High.
1
Read Data FIFO Empty. High only when the read data
FIFO is empty.
Read Data FIFO Almost Empty. High only when the read
1
data FIFO is almost empty. Controlled by the
C_VFBC<Port_Num>_RD_AEMPTY_WD_AFULL_COUNT
parameter.
Notes:
1. The VFBC Reset and Flush inputs must be held High for at least two MPMC_Clk0 cycles. Because these inputs could be controlled from
a different clock domain than the MPMC_Clk0, the relative frequency of the reset/flush clock domain must be taken into account when
determining the number of clock cycles to assert the reset or flush and to wait after reset or flush. The following equation is used to
determine the number of clock cycles to hold the reset or flush input High: 2*(VFBC_Clk_Freq/MPMC_Clk0_Freq)
2. After reset, there should not be any accesses to the VFBC interfaces for 6 MPMC_Clk cycles.
3. After flush, there should not be any accesses to the VFBC interfaces for 6 MPMC_Clk cycles.
DS643 February 22, 2013
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Product Specification