DS643 Datasheet, PDF (59/216 Pages) Xilinx, Inc – Soft Direct Memory Access (SDMA) support

LogiCORE IP Multi-Port Memory Controller (v6.06.a)
The following subsections describe the Control Path/Arbiter:
• Transfer Types
• Arbitration Algorithms
• Arbiter Pipeline
• Control Path and Arbiter Block RAM Utilization
Transfer Types
The control path supports the following transfer types:
• Word reads and writes (32-bit NPI only).
• Double-word reads and writes (64-bit NPI only).
• 4-word, cacheline reads and writes.
• 8-word, cacheline reads and writes.
• 16-word, burst reads and writes.
• 32-word, burst reads and writes.
• 64-word, burst reads and writes. (Not supported in all configurations. See Restrictions on 64-Word Burst
Transfers, page 173 for more information.)
Arbitration Algorithms
The MPMC supports configure-able arbitration algorithms. See MPMC Optimization, page 190 for more
information.
Arbiter Pipeline
An optional pipeline is allowed in the arbitration logic. To achieve best timing, enable this pipeline using the IP
Configuration interface. Enabling the arbiter pipeline could also increase latency. See the “Arbitration” information
in IP Configuration Graphical User Interface, page 209 for more information.
Control Path and Arbiter Block RAM Utilization
The MPMC control logic is designed around a block RAM-based state machine; therefore, the control logic always
consumes one block RAM.
The arbiter uses one block RAM when a custom arbitration algorithm is used. With Fixed or Round Robin
arbitration, or when C_NUM_PORT is set to 1, no additional block RAM is needed.
The MPMC control logic does not support row or bank management. After each NPI transaction, the row and bank
that was accessed is closed with a precharge.
Clock Logic
Spartan-3, Virtex-4, and Virtex-5 FPGA Clock Logic
The MPMC has four system clock inputs and one clock for each PIM. Depending on the MPMC configuration, not
all system clocks must be connected.
Note: For behavioral simulation, the MPMC_Clk and all <PIM>_Clks must be completely phase-aligned. This requirement is
not as strict for actual implementation because any clock skew is correctly analyzed by static timing analysis tools.
DS643 February 22, 2013
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Product Specification