DS643 Datasheet, PDF (143/216 Pages) Xilinx, Inc – Soft Direct Memory Access (SDMA) support

LogiCORE IP Multi-Port Memory Controller (v6.06.a)
SDMA Interrupt Coalescing and Delay Timer
The delay timer is required because of interrupt coalescing in the DMA. For example, if the Rx coalescing counter
is set to 10, an interrupt event is generated for every 10 packets received. If five packets are received on the ethernet
and the channel then goes idle (no traffic), the CPU never processes the five packets because no interrupt was
generated and this interrupt happens only when (or if) five more packets arrive.
To avoid this latency, a timer must fire when a packet has been received, some configurable time has elapsed, and
there are no more packets received during this time.
The purpose of this timer is to avoid large latencies in the received packet (which is sitting in main memory) from
being processed by the CPU when there is non-continuous traffic.
As shown in Figure 25, the Clock Divider module uses a 10-bit value, C_PRESCALAR, to determine how many
LocalLink clock cycles to count before generating a single Timer_ce pulse. For a typical LocalLink clock speed of
200 MHz and C_PRESCALAR=1023, this translates to a 5.12 µs Timer_ce period. Therefore, the 8-bit timer can count
up to a maximum of 256*5.12 = 1.3 ms, before generating an interrupt.
When the Coalescing Counter fires, the delay timer clears automatically.
X-Ref Target - Figure 25
Timer_int
OR
(IRQ_REG.CoalIrq AND CHNL_CTRLIrqCoalEn)
OR
LinkSOF
OR
Channel_Reset
OR
CHNL_CTRL.IRQTimout=0
Timer_rst: set to 0
Link_EOF: sets to 1
Timer_ce_mask
RST
CE
=
Timer_int _lncr
LLink_Clk
Clock Timer_ce
Divider
IRQ_REQ_WE AND IRQ_REG.DlyIRQ
Figure 25: Delay Timer Interrupt Scheme
Decr
DS643_26_071307
The Interrupt Coalescing counter is an additional mechanism for interrupt handing. It can relieve the need for the
CPU to service an interrupt at the end of every packet. Instead, a pre-loadable number of interrupt events (up to
256) generate a single interrupt to the CPU. Figure 26 shows the mechanism used for the Tx coalescing counter
interrupt generation.
DS643 February 22, 2013
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143
Product Specification