DS643 Datasheet, PDF (131/216 Pages) Xilinx, Inc – Soft Direct Memory Access (SDMA) support

LogiCORE IP Multi-Port Memory Controller (v6.06.a)
Transmit Channel Operation
The following steps are required to execute a packet transmit operation:
1. The software creates a chain of descriptors:
a. Specify in the descriptor the packet boundaries using the STS_CTRL_APP0.SOP and STS_CTRL_APP0.EOP
bits.
b. Specify the address to the data buffer to transmit in the CURBUF_ADDR field.
c. Specify the amount of data to transfer for each descriptor in the CURBUF_LENGTH field.
d. Specify a pointer to the next descriptor in NXTDESC_PNT.
2. Software prepares the DMA Channel registers (Order of steps a and b are not critical):
a. Set up interrupts if so desired by writing to the TX_CHNL_CTRL register, specifying interrupt coalescing
information (if enabled).
b. Set a pointer to the first descriptor in the TX_CURDESC_PTR register.
3. The software starts SG automation by writing the pointer to the last descriptor to fetch into the TAILDESC_PTR
register.
4. SDMA requests the first descriptor pointed to by the TX_CURDESC_PTR register.
5. Upon completion of the descriptor fetch, the DMA cycle begins.
6. If the currently fetched descriptor has STS_CTRL_APP0.EOP set, the data of that descriptor is transmitted and
the Master completes the packet on the LocalLink with and End of Payload, (EOP) and End of Frame (EOF). If
the currently fetched descriptor does NOT have STS_CTRL_APP0.EOP set the packet continues.
7. At the completion of each descriptor the channel register information is updated to the corresponding
descriptor memory location.
8. This process continues until the descriptor TX_CURDESC_PTR = TX_TAILDESC_PTR is completed processing.
Receive Channel Operation
The following steps are required to execute a receive operation:
1. The software creates a chain of descriptors.
Note: SDMA supports multiple descriptors being used to describe a single packet. The STS_CTRL_APP0.EOP bit is set
by SDMA in the descriptor associated to the buffer containing the last byte of the received packet.
a. Specify in the CURBUF_ADDR field of each descriptor the address to the start of the associated buffer for
receiving data.
b. Specify in the CURBUF_LENGTH field of each descriptor the available size of the associated buffer for
receiving data. The sum total of the Length field/s in the descriptors must specify a byte count that is large
enough to hold an entire packet.
c. Specify a pointer to the next descriptor in NXTDESC_PNT field.
2. The software prepares the DMA Channel registers (Order of steps a and b are not critical):
a. Set the pointer to the first descriptor in RX_CURDESC_PTR register.
b. Set up Interrupts if required by writing to the RX_CHNL_CTRL register, specifying interrupt coalescing
information (if enabled).
3. The software starts SG Automation by writing the pointer to the last descriptor to fetch into the
RX_TAILDESC_PTR register.
4. SDMA requests the first descriptor pointed to by the RX_NXTDESC_PTR register. For receive channels, the User
Application fields are updated in the descriptor during the descriptor update phase of processing.
5. Upon completion of the descriptor fetch, the DMA cycle begins.
This process continues until the descriptor RX_CURDESC_PTR = RX_TAILDESC_PTR has completed processing.
DS643 February 22, 2013
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Product Specification