DS643 Datasheet, PDF (102/216 Pages) Xilinx, Inc – Soft Direct Memory Access (SDMA) support

LogiCORE IP Multi-Port Memory Controller (v6.06.a)
MIG Virtex-4 FPGA Design Considerations
For Virtex-4 FPGA systems using the MIG PHY, instantiation of IDELAY controllers (IDELAYCTRL) is required to
ensure that the IDELAY elements in the MPMC physical interface behave properly.
The MPMC core parameter, C_NUM_IDELAYCTRL, determines the number of IDELAYCTRL elements to instantiate.
By default, the MPMC instantiates one IDELAYCTRL without a location constraint (LOC), which causes the ISE
implementation tools to replicate the IDELAYCTRL blocks across the entire FPGA.
For Virtex-5 and Virtex-6 FPGAs, the parameter, C_IODELAY_GRP identifies the IDELAYCTRL groupings for the
MAP tool to correctly place these elements so the parameters C_NUM_IDELAYCTRL and C_IDELAYCTRL_LOC do not
have to be set.
The C_IODELAY_GRP default value is sufficient in most cases, except when two IP blocks have I/Os that share a
common clock region and IDELAYCTRL element. In that case, use the solution described below.
For the Integrated MIG GUI flow, these parameters are passed into the MPMC design from the MIG GUI
automatically, but can be set manually to override these automatic values. See Multiple MPMC IDELAYCTRL IP
Designs for an explanation of a special case when this mechanism alone does not work.
Single MPMC IDELAYCTRL Designs
For Virtex-5 FPGA designs and Virtex-4 FPGA designs with the MAP-timing option enabled, MAP trims
unnecessary IDELAYCTRLs. The default setting is sufficient for systems where there is one MPMC instance only,
and no other IP in the system requires the use of IDELAY elements.
Multiple MPMC IDELAYCTRL IP Designs
For systems where there are multiple IP cores each using their own IDELAYCTRL element independently, such as
two instances of MPMC or MPMC and PCI™ in the same system, special consideration must be given to the
number of IDELAYCTRLs.
• Instantiate the correct number of IDELAYCTRL blocks for each IP as determined by the clock regions where the
associated IDELAY elements are used. For these systems, it is necessary to set the correct value for
C_NUM_IDELAYCTRL.
• Ensure the IDELAYCTRL element is associated with the correct clock region positions in the FPGA and is
located using the C_IDELAYCTRL_LOC parameter.
For example, a design requiring two IDELAYCTRLs might have a core configuration of:
PARAMETER C_NUM_IDELAYCTRL = 2
PARAMETER C_IDELAYCTRL_LOC = IDELAYCTRL_X0Y4-IDELAYCTRL_X1Y3
Consult the ISE tool documentation for more information about IDELAYCTRL. The link to ISE tool documentation is
available in Reference Documents, page 215.
The MPMC contains the following I/O signals (see Table 3, page 7) that can be used to chain the IDELAY elements
between IP blocks:
• MPMC_Idelayctrl_Rdy_I is AND’ed with internal IDELAYCTRL instance(s) RDY signal(s) inside the MPMC
and signifies that memory initialization can begin.
• MPMC_Idelayctrl_Rdy_O port signals that the internal IDELAYCTRL instance(s) RDY signal(s) and the
MPMC_Idelayctrl_Rdy_I are all high.
This is useful in situations where two IP blocks have I/O that share a common clock region and IDELAYCTRL
element.
DS643 February 22, 2013
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Product Specification