DS643 Datasheet, PDF (155/216 Pages) Xilinx, Inc – Soft Direct Memory Access (SDMA) support

LogiCORE IP Multi-Port Memory Controller (v6.06.a)
• The IPLB SUBTYPE is chosen when the PIM is connected to a PowerPC 405 processor IPLB1 port using a
point-to-point connection. When this sub type is chosen, the write FIFO logic in the MPMC datapath is also
disabled (C_PI<Port_Num>_WR_FIFO_TYPE = DISABLED).
• The Single SUBTYPE is chosen when the PIM is connected to a PLB bus where all masters are not burst
capable. This is primarily selected in MicroBlaze processor systems where the PIM is connected to a bus with
MicroBlaze processor IPLB and DPLB ports.
• The PLB SUBTYPE is chosen in all other cases. This PLB PIM supports the full set of PLB transactions.
You can find information regarding the PIM SUBTYPES in Configuring PLB v4.6 PIM SUBTYPES, page 156.
Supported NPI Transfer Types
Based on the setting of C_SPLB<Port_Num>_NATIVE_DWIDTH, the PLB v4.6 PIM can generate only certain types of
NPI transfers, as shown in Table 80.
Table 80: Supported Transactions Based on PIM Subtype and Native Width
C_SPLB<Port_Num>_NATIVE_DWIDTH=32
C_SPLB<Port_Num>_NATIVE_DWIDTH=64
Transaction Type
C_PIM<Port_Num>_SUBTYPE
PLB DPLB IPLB Single
Transaction Type
C_PIM<Port_Num>_SUBTYPE
PLB DPLB⁽¹⁾ IPLB⁽¹⁾ Single
Supported
Supported
Single
Read
Y
N
N
Write
Y
N
N
Y
Single
Y
Read
Y
Y
Write
Y
Y
N
Y
N
Y
Read
Y
N
N
4-wd Cacheline
Write
Y
N
N
N
Read
Y
N
4-wd Cacheline
N
Write
Y
N
Y
N
N
N
Read
Y
N
N
8-wd Cacheline
Write
Y
N
N
N
Read
Y
Y
8-wd Cacheline
N
Write
Y
Y
Y
N
N
N
Read
Y
N
N
16-wd Burst
Write
Y
N
N
N
Read
N
N
16-wd Burst
N
Write
N
N
N
N
N
N
Read
N
N
N
32-wd Burst
Write
N
N
N
N
Read
Y
N
32-wd Burst
N
Write
Y
N
N
N
N
N
Notes:
1. Point-to-point configuration is required for the DPLB and IPLB subtypes where the C_SPLB<Port_Num>_NATIVE_DWIDTH=64.
DS643 February 22, 2013
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Product Specification