DS643 Datasheet, PDF (161/216 Pages) Xilinx, Inc – Soft Direct Memory Access (SDMA) support

LogiCORE IP Multi-Port Memory Controller (v6.06.a)
PPC440MC Burstwidth and Burstlength by Memory Type/Width Dependencies
Table 84 shows the required setting for Burstwidth and the allowable settings for Burstlength in relation to memory
type and width.
Table 84: Burstwidth and Burstlength by Memory Type and Width
Memory Type
Memory Width
Required Setting for
Burstwidth Field of PPC440
MI_Control Register⁽¹⁾
Allowable Settings for Burstlength
Field of PPC440 MI_Control Register
SDRAM
8
32
SDRAM
16
32
SDRAM
32
32
SDRAM
64
64
DDR/DDR2
8
32
DDR/DDR2
16
32
DDR/DDR2
32
64
DDR/DDR2
64
64
4, 8
4, 8
4, 8
2, 4, 8
4, 8
4, 8
2, 4, 8
4, 8
Notes:
1. The MPMC datapath architecture does not support a native 128 bit NPI interface for the PPC440MC PIM; therefore, the
maximum datapath width between the MPMC and the PowerPC 440 processor block MC interface is limited to 64 bits.
This might limit the performance gain seen between 32-bit and 64-bit DDR/DDR2. The ppc440mc_ddr2 IP core does
not have this limitation and supports a full 128-bit datapath with a 64-bit DDR2 memory.
Video Frame Buffer Controller PIM
The Video Frame Buffer Controller (VFBC) allows a user IP to read and write data in two dimensional (2D) sets
regardless of the size or the organization of external memory transactions. The VFBC can be used in video
applications where hardware control of 2D data is needed to achieve real time operation.
Typical video applications are: motion estimation, video scaling, onscreen displays, and video capture used in
video surveillance, video conferencing, and video broadcast.
The following subsections describe:
• VFBC Features
• VFBC Overview
• VFBC Command Interface
• VFBC Write Data Interface
• VFBC Read Data Interface
• VFBC Transfer Examples
• VFBC Synthesis Considerations
• VFBC Timing Constraints
VFBC Features
• 2D data transfers (32,640 bytes x 16,777,216 lines maximum and two 32-bit words minimum).
• Independent Write and Read transfer operations.
• Asynchronous FIFO command interface.
• Separate asynchronous FIFO Write and Read data interfaces.
• Configurable 32- or 64-bit NPI data width.
DS643 February 22, 2013
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Product Specification