DS643 Datasheet, PDF (149/216 Pages) Xilinx, Inc – Soft Direct Memory Access (SDMA) support

LogiCORE IP Multi-Port Memory Controller (v6.06.a)
If there is no halt condition, the address contained in the Next Descriptor Pointer register is evaluated as follows:
• If a NULL (0x00000000) is contained in the Next Descriptor Pointer register, the SDMA engine stops
processing buffer descriptors.
• If the address contained in the Next Descriptor Pointer register is not 8-word aligned or reaches beyond the
range of available memory, the SDMA halts processing and sets the SDMA_ERROR bit in the respective status
register (TX_CHNL_STATUS or RX_CHNL_STATUS).
• If the Next Descriptor Pointer register contains a valid address, the contents are moved to the respective
Current Descriptor register (TX_CURDESC_PTR or RX_CUR_DESC_PTR).
Then the SDMA begins another DMA transaction. Table 71 describes the Next Description Pointer (TX_ and RX_)
register bits.
Table 71: Next Descriptor Pointer Register Description
Bit(s)
Name
Core
Access
Reset Value
Description
0:31
TX_NXTDESC_PTR
and RX_NXT_DESC_PTR
Read
0x00000000
8 word aligned pointer to the next buffer descriptor in the chain.
If NULL (0x00000000), DMA engine stops processing buffer
descriptors.
Current Buffer Address (TX_CURBUF_ADDR and RX_CURBUF_ADDR)
Offsets: 0x04 and 0x24
The Current Buffer Address register, one for transmit and one for receive, maintains the contents of the address in
memory where the DMA operation is conducted next. This value is originally loaded into the SDMA when the
descriptor is read by the SDMA.
When set by the current buffer descriptor, the SDMA periodically transfers this value to an internal Address
Counter that then updates the value for each DMA transaction completed.
Upon termination of the transaction, the SDMA overwrites the value of the Current Buffer Address register with
the last value of the Address Counter.
This process continues repeatedly until the SDMA has completed the current descriptor. The reason for this
mechanism is so the SDMA can maintain multiple temporal channels of DMA at a substantially reduced hardware
cost. It is not recommended that software use the Current Buffer Address register to determine SDMA progress
because it changes dynamically. Table 72 describes the Current Buffer Address register bits.
Table 72: Current Buffer Address Register Description
Bit(s)
Name
Core
Access
Reset Value
Description
TX_CURBUF_ADDR
0:31 and
RX_CUR_BUF_ADDR
Read
0x00000000
Address to the current buffer being processed by
SDMA.
Current Buffer Length (TX_CURBUF_LENGTH, RX_CURBUF_LENGTH)
Offsets:0x08 and 0x28
The Current Buffer Length register, one for transmit and one for receive, maintains the contents of the remaining
length of the data to be transferred by the SDMA. The value is originally loaded into the SDMA when the descriptor
is read by the SDMA. When set by the current descriptor, the SDMA periodically transfers this value to an Internal
Length Counter, which then updates the value for each DMA transaction completed. Upon termination of the
transaction, the SDMA overwrites the value of the Current Buffer Length register with the last value of the internal
length counter. This process continues repeatedly until the SDMA has completed the current descriptor. Table 73
describes the Current Buffer Length register bits.
DS643 February 22, 2013
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Product Specification