DS643 Datasheet, PDF (142/216 Pages) Xilinx, Inc – Soft Direct Memory Access (SDMA) support

LogiCORE IP Multi-Port Memory Controller (v6.06.a)
SDMA Interrupts and Errors
The following subsections describe DMA interrupts and errors:
• SDMA Controller Interrupt Description
• SDMA Error Events
• SDMA Interrupt On End Event
• SDMA Interrupt Coalescing and Delay Timer
• SDMA Engine Reset
SDMA Controller Interrupt Description
Each channel can generate one or more events. The interrupt registers (IRQ_REG) report events for the individual
channels; see Figure 24.
X-Ref Target - Figure 24
Channel
Events
IRQ_REG
Channel
Interrupt
Event
Bus
DS643_25_071307
Figure 24: Interrupt Status Register
The IRQ_REG register generates a system interrupt when ERRIrq, DlyIrq, or ClscIrq is set and the corresponding
enable bit is set in the CHANNEL_CTRL register.
Reading the individual IRQs allows the software to determine which event occurred and for which channel the
event was logged. Writing a 1 to the bit position of the event that was logged either clears that event, in the case of
the IRQ_REG.ErrIrq interrupt, or decreases the ClscCnt or DlyCnt, depending upon to which bit the data is
written. When the IRQ_REG.ClscCnt is zero, the IRQ_REG.ClscIrq is cleared to zero. Likewise, when the
IRQ_REG.DlyCnt is zero, the IRQ_REG.DlyIrq is cleared to zero.
SDMA Error Events
An error event occurs when an error is detected during SDMA operations. If an error is detected, IRQ_REG.ErrIrq
is set, and if CHANNEL_CTRL.IrqEn = 1 and CHANNEL_CTRL.IrqErrEn = 1, the DMA Controller also generates
an interrupt, or increases the Coalescing Event counter. This event can be cleared by writing a 1 to
IRQ_REG.ErrIrq.
When a DMA transfer error occurs for a particular channel, that channel is shut down and no more DMA
processing occurs for that channel.
SDMA Interrupt On End Event
An Interrupt On-End Event (IOE) occurs when SDMA has completed processing of a buffer descriptor with the IOE
bit set in the STS_CTRL_APP0 field or an end of packet (EOP) is received or transmitted. If the DMA has completed
operations, the IRQ_REG.CoalIrq is set and, if enabled, an interrupt is also generated. Otherwise, the Coalescing
Event counter increases.
DS643 February 22, 2013
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Product Specification