DS643 Datasheet, PDF (81/216 Pages) Xilinx, Inc – Soft Direct Memory Access (SDMA) support

LogiCORE IP Multi-Port Memory Controller (v6.06.a)
Table 57 shows the C_PM_SHIFT_BY relationship of Bin Number to Transaction Length.
Table 57: Bin Number and Translation Length Relationship
C_PM_SHIFT_BY
Bin Number
Transaction Length
(cycles)
0
0
1
1
0
…
…
31
31+
0
0-1
1
2-3
1
…
…
31
62-63+
0
0-3
1
4-7
2
…
…
31
124-127+
0
0-7
1
8-15
3
…
…
31
248-258+
Configurable Physical Interface
The MPMC Physical Interface (PHY) is the interface situated between memory and the MPMC address path,
control path, and datapath. The PHY interface can be configured to support SDRAM, DDR SDRAM, and DDR2
SDRAM memories across Virtex-4, Virtex-5, and Spartan-3/3A/3E/3AN/3A DSP devices.
DDR2 SDRAM, and DDR3 SDRAM are supported on Virtex-6 FPGAs only. Low Power DDR (LPDDR - also known
as Mobile DDR) is not supported by any PHY interface on these architectures.
The following subsections describe these topics:
• Available PHY Interface by Device: Provides the by-device memory type support.
• Connecting Memory to the PHY Interface: Provides a table of the signals and parameters per PHY layer.
• Memory Interface Generator PHY Interface: (MIG)-based PHY interface is a DDR/DDR2/DDR3 physical
memory interface core/reference design technology used by MPMC. See Reference Documents, page 215 for
links to more information about MIG. This is the recommended PHY interface. Using MIG-based PHY requires
that you follow the MIG FPGA pinout and board layout guidelines. You must use the MIG tool to generate
pinout, placement, and timing constraints (UCF constraints) for MPMC designs.
• Static PHY Interface: Use the Static PHY when MIG pinout and layout guidelines were not followed. The Static
PHY is currently available for SDRAM, DDR, and DDR2 memories except on Virtex-6 FPGAs.
• SDRAM PHY Interface: The interface between the Single Data Rate Access Memory (SDRAM) and the MPMC
control path, address path, and datapath. The SDRAM PHY interface supports Virtex-4, Virtex-5, and
Spartan-3/3E/3A/3AN/3A DSP devices.
The MPMC can read and write to Mobile SDRAM devices, but the MPMC does not make use of the low power
features of Mobile SDRAM, such as deep power down or partial-array refresh. The SDRAM PHY makes use of
the Static PHY logic for data capture.
DS643 February 22, 2013
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81
Product Specification