DS643 Datasheet, PDF (183/216 Pages) Xilinx, Inc – Soft Direct Memory Access (SDMA) support

LogiCORE IP Multi-Port Memory Controller (v6.06.a)
32-Word, Burst Read with Read FIFO Flush Asserted
Figure 52 shows the following:
• A 64-bit NPI.
• An 18-word, burst Read transfer (a 32-word burst Read transfer that is terminated by RdFIFO_Flush.)
• The address is acknowledged in the same cycle as it is requested.
• The address is on a 32-word boundary.
• There are three cases of possible RdFIFO_Latency values.
X-Ref Target - Figure 52
MPMC_CLK0
AddrReq
AddrAck
Addr[31:0]
0x80
RNW
Size[3:0]
0x4
RdModWr
InitDone
RdFIFO_Empty
RdFIFO_Pop
RdFIFO_Flush
RdFIFO_Latency[1:0]
RdFIFO_Data[63:0]
RdFIFO_RdWdAddr[3:0]
RdFIFO_Latency[1:0]
RdFIFO_Data[63:0]
RdFIFO_RdWdAddr[3:0]
RdFIFO_Latency[1:0]
RdFIFO_Data[63:0]
RdFIFO_RdWdAddr[3:0]
0x0
D0
D1
D2
D3
D4
D5
D6
D7
D8
0x1
D0
D1
D2
D3
D4
D5
D6
D7
D8
0x2
D0
D1
D2
D3
D4
D5
D6
D7
D8
Figure 52: 64-Bit NPI 32-Word Burst Read with Read FIFO Flush Asserted
Case 1
Case 2
Case 3
DS643_45_072407
DS643 February 22, 2013
www.xilinx.com
183
Product Specification