DS643 Datasheet, PDF (36/216 Pages) Xilinx, Inc – Soft Direct Memory Access (SDMA) support

LogiCORE IP Multi-Port Memory Controller (v6.06.a)
Virtex-4 FPGA MIG PHY Debug Registers
Table 32: Virtex-4 FPGA MIG PHY Debug Registers
Register Name
Base Address/
Offset from
C_MPMC_CTRL
BASEADDR (in hex)
Bits
0:31
Field Name
0:5 unused
Access
Type
6 IDELAYCTRL_RDY_O
R
7 IDELAYCTRL_RDY_I
R
V4_CALIB_REG
0x2100 8:12 unused
13 FORCE_INITDONE
R/W
14 FORCE_INITDONE_VAL
R/W
15 MIG_INIT_DONE
R
V4_CALIB_REG
0x2100
16:30 unused
31 HW_CALIB_ON_RESET
R/W
0:5 unused
6 SEL_DONE
R
V4_CALIB_STATUS 0x2104
7:15 DONE_STATUS
R
16:22 unused
23:31 ERR_STATUS
R
Default
Value
0
0
0
0
0
1
0
0
0
Description
Status of MPMC_Idelayctrl_Rdy_O
0 = not ready
1 = ready
Status of MPMC_Idelayctrl_Rdy_I
0 = not ready
1 = ready
1 = Force MPMC INIT_DONE signal to be
equal to FORCE_INITDONEVAL
0 = Allow hardware calibration engine to
drive MPMC INIT_DONE signal
Value to set MPMC INIT_DONE when
FORCE_INITDONE = 1.
0 = not done
1 = done
0 = incomplete
1 = MIG_HW_CALIBRATION initialization
is complete.
Note: HW calibration could be
complete but the INIT_DONE
signal from the PIM might be
masked by the FORCE_INITDONE
signal.
Related MIG PHY signal:
PHY_INIT_DONE
Calibrate HW upon reset.
0 = Do not run hardware calibration
engine upon MPMC reset
1 = Start memory hardware calibration
engine upon MPMC reset
Indicates calibration process of
center-aligning DQS with respect to clock
is complete.
0 = not done
1 = done
Related MIG PHY signal: SEL_DONE
Tap control and pattern compare
calibration completion status, 1 bit plus 1
bit per DQS bit.
0 = calibration not complete
1 = calibration complete
Related MIG PHY signals: COMP_DONE
COMP_ERROR
4-bit calibration error status.
0 = error
1 = no error
Related MIG PHY signal: COMP_ERR
DS643 February 22, 2013
www.xilinx.com
36
Product Specification